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Copyright © 2011 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
7. CIRCUIT DIAGRAM
12
11
10
9
8
7
6
5
4
3
2
1
H
G
F
E
D
C
B
A
H
G
F
E
D
C
B
A
12
11
10
9
8
7
6
5
4
3
2
1
2V8_RF
1n
C202
10K
R201
68K
PT200
10n
C205
100n
C200
200K
R203
2V8_TCXO
33
R202
U200
NL17SZ04XV5T2G
3
4
2
5
VCC
GND
2V8_TCXO
10n
C201
100n
C204
33n
C203
100
R200
19.2MHz
X200
TG-5025CG-19_2M
3
2
6
5
4
1
VC
VCC
TP1
TP2
GND
OUT
10n
C206
10n
C208
10n
C207
10n
C209
1n
C210
100n
C218
100n
C219
100n
C217
1n
C211
10u
C213
100n
C221
100n
C222
100n
C220
100n
C225
100n
C224
100n
C223
6040
R205
6040
R204
1n
C216
1n
C215
1n
C227
1n
C226
100n
C212
100n
C214
L2000
U201
3
1
E
2
1
E
6
F
5
F
3
C
2
D
2
C
1
1
E
2
B
6
K
6
J
2
G
3
E
2
E
4
1
C
5
1
C
4
1
B
4
1
E
6
1
C
6
G
3
J
3
K
2
L
2
K
2
J
H23
J5
H1
AL18
AL3
P8
N8
N9
P9
T3
R3
T1
R1
R2
T2
E20
E21
F21
F20
E16
E17
E18
E19
E5
D3
D1
E15
C13
M2
M1
L1
K1
J1
L3
M3
F3
H3
H2
1
N
3
2
M
2
N
3
2
K
3
2
J
4
2
J
4
2
H
4
2
G
4
2
F
4
2
E
4
2
D
4
2
C
4
2
B
4
2
A
3
2
B
2
2
B
1
2
B
0
2
B
9
1
B
8
1
B
7
1
B
6
1
B
6
C
5
C
1
1
B
0
1
B
9
B
8
B
7
B
6
B
K25
K24
L25
C18
L23
L24
E1
C7
N3
E23
D23
G23
F23
C20
C19
C22
C21
C11
C10
C9
C8
B25
A25
D25
C25
E25
F25
H25
G25
A17
A16
A19
A18
A20
A21
A23
A22
A5
A4
A6
A7
A9
A8
A10
A11
TRF0_OUTP
TRF0_OUTN
TRF1_OUTP
TRF1_OUTN
TRF2_OUTP
TRF2_OUTN
TRF3_OUTP
TRF3_OUTN
RRFM0_INP
RRFM0_INN
RRFM1_INP
RRFM1_INN
RRFM2_INP
RRFM2_INN
RRFM3_INP
RRFM3_INN
RRFD0_INP
RRFD0_INN
RRFD1_INP
RRFD1_INN
RRFD2_INP
RRFD2_INN
RRFD3_INP
RRFD3_INN
EXT_TBB_IP
EXT_TBB_IN
EXT_TBB_QP
EXT_TBB_QN
EXT_RBBM_QP
EXT_RBBM_QN
EXT_RBBM_IP
EXT_RBBM_IN
EXT_RBBD_QP
EXT_RBBD_QN
EXT_RBBD_IP
EXT_RBBD_IN
TBB_LDO_O
TRF_VCC
TBB_VCC
RBBM_LDO_O
RBBM_VCC
RRFM_VCC
RBBD_LDO_O
RBBD_VCC
RRFD_VCC
1
_
2
D
N
G
_
F
R
T
2
_
2
D
N
G
_
F
R
T
3
_
2
D
N
G
_
F
R
T
4
_
2
D
N
G
_
F
R
T
5
_
2
D
N
G
_
F
R
T
6
_
2
D
N
G
_
F
R
T
1
_
D
N
G
_
F
R
T
2
_
D
N
G
_
F
R
T
1
_
D
N
G
_
M
F
R
R
2
_
D
N
G
_
M
F
R
R
3
_
D
N
G
_
M
F
R
R
4
_
D
N
G
_
M
F
R
R
5
_
D
N
G
_
M
F
R
R
6
_
D
N
G
_
M
F
R
R
7
_
D
N
G
_
M
F
R
R
8
_
D
N
G
_
M
F
R
R
1
_
D
N
G
_
D
F
R
R
2
_
D
N
G
_
D
F
R
R
3
_
D
N
G
_
D
F
R
R
4
_
D
N
G
_
D
F
R
R
5
_
D
N
G
_
D
F
R
R
6
_
D
N
G
_
D
F
R
R
7
_
D
N
G
_
D
F
R
R
8
_
D
N
G
_
D
F
R
R
9
_
D
N
G
_
D
F
R
R
D
N
G
_
D
B
B
R
D
N
G
_
M
B
B
R
D
N
G
_
O
D
L
_
B
B
T
D
N
G
_
O
D
L
_
B
B
R
D
N
G
_
O
D
L
_
E
F
A
AFE_REFTOP
AFE_REFBOT
AFE_CML
AFE_COMP
AFE_VBGR
AFE_VDD12A0
AFE_VDD12A1
AFE_VDD12A2
AFE_LDO_O_1
AFE_LDO_O_2
RPLL_TEST1
RPLL_TEST2
TPLL_TEST1
TPLL_TEST2
AFC_VOUT
LNA0_PORT0_EN
LNA0_PORT1_EN
LNA0_PORT2_EN
LNA0_PORT3_EN
LNA1_PORT0_EN
LNA1_PORT1_EN
LNA1_PORT2_EN
LNA1_PORT3_EN
PORT0_PA_EN
PORT1_PA_EN
PORT2_PA_EN
PORT3_PA_EN
PA_MODE0
PA_MODE1
BAND_SEL0
GPIO29/BAND_SEL1
GPIO28/BAND_SEL2
GPIO27/BAND_SEL3
I_REF_CLK
B_PLL_FILTER
REF_CLK_IN
REFCLK_OUT_PAD
BG_REF_EXT
0
A
2
1
D
N
G
_
E
F
A
1
A
2
1
D
N
G
_
E
F
A
2
A
2
1
D
N
G
_
E
F
A
R
A
5
2
D
N
G
_
E
F
A
A
5
2
D
N
G
_
E
F
A
2
1
D
N
G
_
E
F
A
D
N
G
_
O
L
R
D
N
G
_
K
L
U
B
R
1
_
D
N
G
_
L
L
P
R
2
_
D
N
G
_
L
L
P
R
3
_
D
N
G
_
L
L
P
R
1
_
D
N
G
_
B
B
T
2
_
D
N
G
_
B
B
T
D
N
G
_
F
E
R
H
D
N
G
_
F
E
R
D
N
G
_
C
F
R
D
N
G
_
O
L
T
D
N
G
_
K
L
U
B
T
1
_
D
N
G
_
L
L
P
T
2
_
D
N
G
_
L
L
P
T
3
_
D
N
G
_
L
L
P
T
1
_
A
5
2
D
N
G
_
C
F
A
2
_
A
5
2
D
N
G
_
C
F
A
1
_
D
N
G
_
G
2
_
D
N
G
_
G
1V1_TX
1V1_RXM
LNA0_MODE1
RRFM1_INP
PA_EN1
PA_MODE0
PA_MODE1
TRF1_OUTN
TRF1_OUTP
RRFD1_INN
BB_TEMP
TCXO_IN
TCXO_IN
AFC_OUT
AFC_OUT
REF_CLK_OUT
REF_CLK_OUT
RRFD1_INP
RRFM1_INN
L2000
VCTCXO
BB TEMP