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Lenze · 8400 HighLine · Reference manual · DMS 12.0 EN · 06/2017 · TD23
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17
Function library
17.1
Function blocks | L_DFlipFlop_2
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If the
bClr
input = TRUE:
• Due to the priority
bClr
>
bClk
,
bD
the
bOut
output signal can be set any time to the
FALSE
status
by the
bClr
input signal = TRUE.
• The output signal is kept in this status independent of the other input signals.
17.1.71
L_DFlipFlop_2
The FB saves binary signals (DFlipFlop) in a clock-controlled way.
Inputs
Outputs
Designator
Data type
Information/possible settings
bD
BOOL
Data input
bClk
BOOL
Clock input
• Only FALSE/TRUE edges are evaluated
bClr
BOOL
Reset input
TRUE
• The
bOut
output is set to FALSE.
• The
bNegOut
output is set to TRUE.
Designator
Data type
Value/meaning
bOut
BOOL
Output signal
bNegOut
BOOL
Output signal, inverted
For a detailed functional description see
/B')OLS)ORSB
E&ON
E&OU
E'
E2XW
E1HJ2XW
4
4
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