crystal User Manual
Version: 6.6.0/2
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19. Configuring Custom Logical Behaviour
19.22
ShiftReg 16
"Logic -> ShiftReg 16"
A
ShiftReg16
element is a logical shift register with 16 outputs. It operates as a series of
with 16
parallel outputs, where the output of one flip-flop is connected to the input of the next. They share a single clock
signal which causes the data to shift from one flip-flop to the next. By connecting the last flip-flop back to the
first, using
Ring Mode
, the data can cycle for extended periods.
General Parameters
ShiftReg 16
Enter a reference name for the element.
Input (static)
Assigns the data input which you wish to process.
Clock (pos. edge)
Assigns the clock source. If you leave this field empty, then the system clock will be used
(approximately 60Hz).
Reset (static)
Sets all outputs to be false as long as
Reset Static
is active.
Ring Mode
Enable this option to connect the output of the last flip-flop back to the first (to cycle the data).
The control outputs appear under the “Logic -> <GroupName> -> ShiftReg 16” branch of the 'Tree Selection'
window:
Output 1 to 16
The positive outputs 1 to 16.
nOutput 1 to 16
The negated outputs 1 to 16.
