15-18
LatticeECP2/M sysCONFIG Usage Guide
Figure 15-10. Slave Parallel with Flowthrough
To support asynchronous configuration, where the host may provide data faster than the FPGA can accept it, Slave
Parallel mode can use the BUSY signal. By driving the BUSY signal high the Slave Parallel device tells the host to
pause sending data. Please note that all data and control are still synchronous with CCLK, asynchronous refers to
the ability to throttle the data transfer using BUSY. See Figure 15-11.
Figure 15-11. Parallel Port Write Timing Diagram
The CSN and CS1N pins must remain low while the configuration bitstream is being sent to the device or the con-
figuration will fail. To temporarily stop the write process, the user can pause the CCLK signal and the data. An
example of this is shown in Figure 15-11.
Lattice FPGA
Slave Parallel
CCLK
D[0:7]
DONE
INITN
CSON
CFG1
CFG0
CFG2
CS1N
PROGRAM
BUSY
WRITEN
CSN
PROGRAMN
Lattice FPGA
Slave Parallel
CCLK
D[0:7]
DONE
INITN
CFG1
CFG0
CFG2
CS1N
BUSY
WRITEN
CSN
PROGRAMN
CSON
INITN
DONE
D[0:7]
CCLK
BUSY
WRITEN
FT_RESET
SELECTN
Note: In Slave Parallel mode, the Flowthrough option is not supported when using encrypted bitstream files with the
LatticeECP2/M S-Series devices. Please refer to the
LatticeECP2/M S-Series Configuration Encryption Usage Guide
,
TN1109, for more information about using encrypted bitstream files.
D[0:7]
I
N
IT
N
PROGRAM
N
W
RITE
N
CCLK
BUSY
C
u
rrent Command
W
rite
W
rite
W
rite
N
ext Command
CS
N
CS1
N
W
rite
……
…
N
ote:
W
hen do
w
nloading an encrypted
b
itstream file to the LatticeECP2/M S-Series de
v
ices, the
u
ser m
u
st
adhere to the appropriate conditions for the CCLK signal. These conditions are sho
w
n in the
LatticeECP2/M
S-Series Config
u
ration Encryption Usage G
u
ide
, T
N
1109.
