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LatticeECP2/M sysCONFIG Usage Guide

Figure 15-9. Slave Parallel with Bypass Option

Lattice FPGA

Slave Parallel

CCLK

D[0:7]

DONE

INITN

DOUT

CFG1

CFG0

CFG2

CS1N

PROGRAM

Lattice FPGA

Slave Serial

DOUT

CFG1

CFG0

CFG2

CCLK

DI/CSSPI0N

DONE

INITN

PROGRAMN

BUSY

WRITEN

CSN

PROGRAMN

WRITEN

BUSY

CLOCK

DATA

DONE

INIT

Select1

Select2

N

ote: In Sla

v

e Parallel mode, the Bypass option is not s

u

pported

w

hen

u

sing encrypted

b

itstream files

w

ith the

LatticeECP2/M S-Series de

v

ices. Please refer to the

LatticeECP2/M S-Series Config

u

ration Encryption Usage G

u

ide

,

T

N

1109, for more information a

b

o

u

t

u

sing encrypted

b

itstream files.

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Summary of Contents for ECP2 Series

Page 1: ...g i e getting ready to receive configuration data Once the LatticeECP2 M has finished initializing the INITN pin will be driven high The low to high transition of the INITN pin causes the CFG pins to be sampled telling the LatticeECP2 M which port it is going to configure from The LatticeECP2 M then begins reading data from the selected port and starts looking for the preamble BDB3 hex All data af...

Page 2: ...ences in Lattice ispLEVER and Diamond software or as HDL source file attributes The LatticeECP2 M also supports ispJTAG for configuration transparent read back and JTAG testing The follow ing sections describe the function of the various sysCONFIG and JTAG pins Table 15 2 is provided for reference Table 15 2 Configuration Pins for the LatticeECP2 M Pin Name I O Type Pin Type Mode Used CFG 2 0 Inpu...

Page 3: ...used to trigger config uration at any time INITN The INITN pin is a bidirectional open drain control pin INITN is capable of driving a low pulse out as well as detect ing a low pulse driven in When the PROGRAMN pin is driven low or a JTAG Reset instruction is received or after the internal Power On Reset signal is released during power up the INITN pin will be driven low to reset the internal conf...

Page 4: ...an output again on the next configuration initialization sequence The MCCLK_FREQ parameter one of the global preferences in the Design Planner of ispLEVER or the Spread sheet View in Diamond controls the CCLK master frequency see data sheet On Chip Oscillator section for the fre quency selection The software default setting for the configuration CCLK is 2 5 MHz For a complete list of the supported...

Page 5: ...pins be driven The CSN and CS1N pins must remain low while the configuration bitstream is being sent to the device or the configuration will fail If SRAM configuration memory needs to be accessed using the parallel pins while the part is in user mode the DONE pin is high then the PERSISTENT preference must be set to ON to preserve these pins as CSN and CS1N CSN and CS1N are not connected in the 10...

Page 6: ...15 6 LatticeECP2 M sysCONFIG Usage Guide using the SPI port while the part is in user mode the DONE pin is high then the PERSISTENT preference must be set to ON to preserve this pin as SISPI ...

Page 7: ... O pins used for data write and read When the WRITEN signal is low and the CSN and CS1N pins are low the D 1 6 pins become data inputs When the WRITEN signal is driven high and the CSN and CS1N pins are low the D 1 6 pins become data outputs If either CSN or CS1N is high D 1 6 will be tri state If SRAM configuration memory needs to be accessed using the parallel pins while the part is in user mode...

Page 8: ...pports hysteresis the typical hysteresis is approximately 100mV when VCCJ 3 3V The TCK pin does not have a pull up A pull down resistor between TCK and ground on the PCB of 4 7 K is recommended to avoid inadvertent clocking of the TAP controller as VCC ramps up When downloading an encrypted bitstream file to the LatticeECP2 M S Series devices the user must adhere to the appropriate conditions for ...

Page 9: ...imum Configuration Bits SPI Flash Mode Bitstream File Table 15 5 Maximum Configuration Bits Serial and Parallel Mode Bitstream File Device Bitstream Size Mb SPI Flash Mb Dual Boot SPI Flash Mb ECP2 6 1 5 2 4 82 ECP2 12 2 9 4 8 ECP2 20 4 5 8 16 ECP2 35 6 3 8 16 ECP2 50 8 9 16 32 ECP2 70 13 3 16 32 ECP2M 20 5 9 8 16 ECP2M 35 9 8 16 32 ECP2M 50 15 8 16 64 ECP2M 70 19 8 32 64 ECP2M 100 25 6 32 64 1 Th...

Page 10: ... Vendor List One FPGA One SPI Flash The simplest SPI configuration consists of one SPI Serial Flash connected to one LatticeECP2 M as shown in Figure 15 1 This is also the recommended method for use when downloading an encrypted bitstream file to the LatticeECP2 M S Series devices Figure 15 1 One FPGA One SPI Serial Flash Multiple FPGA One SPI Flash With a sufficiently large SPI Flash multiple FPG...

Page 11: ...nopera ble Ideally the FPGA should detect that the data is corrupt and boot from a known good or golden boot image This is exactly what SPIm does The golden image is stored at the beginning of the Flash address space the updatable or primary image is above the golden image During configuration if the FPGA detects data corruption in the primary image it will automati cally reboot from the golden im...

Page 12: ...PGA Next open ispVM see Figure 15 3 do a scan of the board by clicking on the SCAN button on the toolbar and then double click on the row in the chain that has the LatticeECP2 M You will now see the Device Information win dow see Figure 15 4 Figure 15 4 Device Information Window From the Device Options drop down box select Dual Boot SPI Flash Programming Then click on the SPI Flash Options button ...

Page 13: ...wer up when the PROGRAMN pin is toggled or when a JTAG Refresh instruction is issued the LatticeECP2 M reads the primary file from SPI Serial Flash If a CRC error is found then the LatticeECP2 M will re boot automatically reading configuration data from the golden file instead of the primary file Note that if an error is found in the golden file the LatticeECP2 M will drive the INITN pin low and s...

Page 14: ...ion Slave Serial Mode In Slave Serial mode the CCLK pin becomes an input receiving the clock from an external device The LatticeECP2 M accepts data on the DI pin on the rising edge of CCLK Slave Serial only supports writes to the FPGA it does not support reading from the FPGA After the device is fully configured if the Bypass option has been set any additional data clocked into DI will be presente...

Page 15: ...ispLEVER Design Planner or in the Diamond Spreadsheet View Global Preferences tab Note SLAVE PARALLEL Mode is not available in the 100 pin TQFP and 208 pin PQFP package offerings since the CSN CS1N and WRITEN pins are not bonded out for these packages Figure 15 8 Parallel Port Read Timing Diagram Lattice FPGA Slave Serial CCLK DI CSSPI0N DONE INITN DOUT CFG1 CFG0 CPU DATA CLK CFG2 PROGRAMN PROGRAM...

Page 16: ...lowthrough command is detected in the bitstream instead of the bypass command the CSON signal will drive the following parallel mode device s chip select low as shown in Figure 15 10 If either type of overflow is active driving both the CSN and CS1N pins high will reset overflow i e take the device out of overflow Frame Contents Description Header 1111 1111 2 Dummy Bytes 10111101 10110011 2 byte P...

Page 17: ...1 CFG0 CFG2 CCLK DI CSSPI0N DONE INITN PROGRAMN BUSY WRITEN CSN PROGRAMN WRITEN BUSY CLOCK DATA DONE INIT Select1 Select2 Note In Slave Parallel mode the Bypass option is not supported when using encrypted bitstream files with the LatticeECP2 M S Series devices Please refer to the LatticeECP2 M S Series Configuration Encryption Usage Guide TN1109 for more information about using encrypted bitstrea...

Page 18: ...ata An example of this is shown in Figure 15 11 Lattice FPGA Slave Parallel CCLK D 0 7 DONE INITN CSON CFG1 CFG0 CFG2 CS1N PROGRAM BUSY WRITEN CSN PROGRAMN Lattice FPGA Slave Parallel CCLK D 0 7 DONE INITN CFG1 CFG0 CFG2 CS1N BUSY WRITEN CSN PROGRAMN CSON INITN DONE D 0 7 CCLK BUSY WRITEN FT_RESET SELECTN Note In Slave Parallel mode the Flowthrough option is not supported when using encrypted bits...

Page 19: ...bedded situations where an on board processor provides the data while con trolling the JTAG signals this is called ispVM Embedded more information can be found in ispVM s help facility IEEE 1532 programming will be slower than the Fast Program mode since it requires a post programming bit by bit verification During JTAG configuration the Boundary Scan cells take control of the LatticeECP2 M I Os T...

Page 20: ...nce completes In parallel mode if Bypass needs to be aborted drive both CSN and CS1N high this acts as a Bypass reset signal Flowthough Option As with Bypass Flowthrough can be set in the Bitgen properties in ispLEVER and in the Strategy Process Options settings To set the Flowthrough option in Diamond see Appendix A The Flowthrough option can be used with par allel daisy chains only The Flowthrou...

Page 21: ... SPI Port pins Setting PERSISTENT ON also sets a hardware fuse So not only are the pins reserved in software they are also reserved in hardware PERSISTENT is set to ON when the user wants to be able to read the SRAM configuration memory using the Slave Parallel port In order to perform a read using the parallel port the user must first send a read command set ting PERSISTENT ON allows the parallel...

Page 22: ...and provides the transition from Configuration Mode to User Mode The Wake Up pro cess begins when the internal Done bit is set Table 15 9 provides a list of the Wake Up sequences supported by the LatticeECP2 M Figure 15 12 shows the Wake Up timing The WAKE_UP defaults work fine for the vast majority of applications To set the WAKE_UP options in Diamond see Appendix A Table 15 9 Wake Up Options Seq...

Page 23: ...t on suc cessful completion of configuration Synchronous to External DONE Pin The DONE pin can be used to synchronize Wake Up to other devices in the configuration chain If DONE_EX see the DONE_OD DONE_EX section above is ON then the DONE pin is a bi directional pin If an external device drives the DONE pin low then the Wake Up sequence will be delayed configuration can complete but Wake Up is del...

Page 24: ...rom www latticesemi com and a Lattice ispDOWNLOAD cable Q I can t read the LatticeECP2 M device ID using JTAG What could be wrong A This is the most basic of JTAG operations If you are having trouble reading the device ID then something basic is wrong Check that the JTAG connections are correct and that VCCJ and the download cable VCC are cor rect and the same Make sure that the XRES pin is connec...

Page 25: ...sh of the 25 type are 3 3V so the Flash and VCCIO8 must be connected to 3 3V Q Can I use something other than a 25 type SPI Serial Flash A Only devices that recognize a read op code of 03h may be used with the LatticeECP2 M Please refer to Table 15 6 for a list of vendors Q My design is small can I use a smaller than recommended SPI Flash A The state of all of the device fuses is contained in the ...

Page 26: ...ugust 2007 01 8 Added sizes for encrypted bitstream files and new conditions for their use Removed restriction on I O direction for dual purpose configuration pins September 2007 01 9 Updated Configuration Pins text section Updated PROGRAMN text section January 2008 02 0 Changed PROGRAMN and INITN pin descriptions Changed CSN and CS1N pin description Added CSN and CS1N pin restrictions in Slave Pa...

Page 27: ...go into the new location but the original source files will not move or be copied The Diamond project will reference the source files in the original location The project files are converted to Diamond format with the default strategy settings Adjusting PCS Modules PCS modules created with IPexpress have an unusual file structure and need additional adjustment when import ing a project from ispLEV...

Page 28: ...do not require regenerating both files Force Module and Settings Generation Generates both the HDL and configuration files Force Settings Generation Only Generates only the attributes file You get an error message if the HDL file also needs to be generated Force Place Route Process Reset Resets the Place Route Design process forcing it to be run again with the newly generated PCS module Force Plac...

Page 29: ...you to experiment with alternative optimization options across a common set of source files Since each strategy may have been processed to different stages this dialog allows you to specify which stage you wish to load 6 In the Add Source page select from the source files listed in the Source Files list box or use the browse button on the right to choose another desired source file Note that if yo...

Page 30: ...es Preference Name Values PERSISTENT ON Off CONFIG_MODE SLAVE_SERIAL JTAG NONE SLAVE_PARALLEL SPI SPIm DONE_OD ON Off DONE_EX OFF MCCLK_FREQ 2 5 5 4 10 34 41 45 CONFIG_SECURE OFF ON WAKE_UP An integer between 1 and 25 COMPRESS_CONFIG OFF ON INBUF OFF ON ENABLE_NDR OFF ON ...

Page 31: ...Diamond To set any of the Bitstream Generation options listed in Table 15 12 do the following In the File List pane double click the left mouse button on a Strategy to invoke the Strategy settings window In the Process pane left click on Bitstream All options related to generating a bitstream can be set in this win dow ...

Page 32: ... the drop down menu Preference Name Values Chain Mode Disable default Bypass Flowthrough Create bit file True No Header True False Output Format Bit File Binary Mask and Readback File ASCII Mask and Radback File Binary Raw Bit file ASCII PROM Data Output Format Intel Hex 32 bit Motorola Hex 32 bit Reset Config RAM in re configuation True False Run DRC True False Search Path Enter a value or browse...

Page 33: ...on Control Pack You must also have selected an encrypted device in your project To Set Security Settings do the following Select the Tools Security Setting option The following dialog box appears If desired select Change and enter a password Select OK A dialog window appears to enter an encryption key If you do not want to enable an encryption key select OK If you do want to enable an encryption k...

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