Lattice Semiconductor MachXO2 Breakout Board, User Manual

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MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-202
2
Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal .
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28 FPGA-EB-02051-2.3
Figure A.4. FPGA
5
5
4
4
3
3
2
2
1
1
NOTE
PLACE ALL 100 OHM
DIFF TERM RESISTORS
ON BOTTOM OF BOARD
MAKE PWR TRACES
CAPABLE OF 1A
MAKE PWR TRACES
CAPABLE OF 1A
50MHz OSC
This is optional
to enable or
disable the
crystal.
PB4A
PB4B
CSSPIN_PB4C
PB4D
PB6A
PB6B
MCLK_CCLK_PB6C
S0_SPISO_PB6D
PB9C
PB9D
PCLKT2_0_PB9A
PCLKC2_0_PB9B
PB11C
PCLKT2_PB11A
PB11D
PCLKC2_PB11B
PB15A
PB15C
PB15B
PB15D
PB18A
PB18B
PB18C
PB18D
PB20A
PB20B
SI_SISPI_PB20D
SN_PB20C
PL2A_L_GPLLT_FB
PL2B_L_GPPLC_FB
PL2C_L_GPLLT_IN
PL2D_L_GPLLC_IN
PL3A_PCLKT3_2
PL3B_PCLKC3_2
PL3C
PL3D
PL4A
PL4B
PL4C
PL4D
PL5A_PCLKT3_1
PL5B_PCLKC3_1
PL5C
PL5D
PL8A
PL8B
PL8C
PL8D
PL10A
PL10B
PL10C
PL10D
PL9A_PCLKT3_0
PL9B_PCLKC3_0
PL3C PL3D
PL4A PL4B
PL4C PL4D
PL5A_PCLKT3_1 PL5B_PCLKC3_1
PL5C PL5D
PL8A PL8B
PL8C PL8D
PL9A_PCLKT3_0 PL9B_PCLKC3_0
PL10B
PL10D
PL10A
PL10C
PL2A_L_GPLLT_FB PL2B_L_GPPLC_FB
PB4A
PB4B
CSSPIN_PB4C
PB4D
PB6A MCLK_CCLK_PB6C
PB6B
PB9C
PB9D PCLKC2_0_PB9B
PB11C PCLKT2_PB11A
PB11D PCLKC2_PB11B
PB15A PB15C
PB15B PB15D
PL2C_L_GPLLT_IN PL2D_L_GPLLC_IN
PB4A
PB4B
CSSPIN_PB4C
PB4D
PB6A
PB6B
MCLK_CCLK_PB6C
S0_SPISO_PB6D
PB9C
PB9D
PCLKT2_0_PB9A
PCLKC2_0_PB9B
PB11C
PB11D
PCLKT2_PB11A
PCLKC2_PB11B
PB15A
PB15C
PB15B
PB15D
PB18A
PB18B
S0_SPISO_PB6D
PCLKT2_0_PB9A
PB18C
PB18D
PB20A
PB20B
SN_PB20C
SI_SISPI_PB20D
PB18A
PB18B
PB18C
SN_PB20C
PB18D
PB20A
PB20B SI_SISPI_PB20D
PL3A_PCLKT3_2 PL3B_PCLKC3_2
PL10A
PL9A_PCLKT3_0
VCCIO3
2
VCCIO2
VCC_3.3V VCCIO3
VCCIO2
+3.3V VCCIO3
VCCIO2 +3.3V
+3.3V
ii TTTitttllleee
ii SSSizzzeee Document Number
aa D D Dattteee::: SSShhheeeeeettt ff ooof
S S AXELSY AXELSY AXELSYS
C C LLLCMXX M MXO O O222---111200ZEE 200Z 200ZE---BBB---EEEVVVN N N BBB
444 555
100 R31 DNI
100
R35 DNI
C53
0.1uF
100 R41 DNI
100 R38 DNI
100
R32 DNI
R37 DNI
J5
Header2x20
DNI
2
4
6
8
10
12
14
16
18
20
24
22
26
28
30
32
34
36
38
40 39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
C28
0.1uF
R28 DNI
X2
CB3LV-3C-50M0000
DNI
EN
1
GND
2
Output
3
Vcc
4
100 R30 DNI
BANK 2 BANK 3
LCMXO2-1200ZE-1TG144C
U3-3 1
PL2A/L_GPLLT_FB
1
PL2B/L_GPPLC_FB
2
PL2C/L_GPLLT_IN
3
PL2D/L_GPLLC_IN
4
VCCIO3 3
7
VCCIO3
4
16
PL3A/PCLKT3_2
5
PL3B/PCLKC3_2
6
PL3C
9
PL3D
10
PL4A
11
PL4B
12
PL4C
13
PL4D
14
NC0
15
NC1
17
PL5A/PCLKT3_1
19
PL5B/PCLKC3_1
20
PL5C
21
PL5D
22
PL8A
23
PL8B
24
PL8C
25
PL8D
26
VCCIO3
30
PL9A/PCLKT3_0
27
PL9B/PCLKC3_0
28
PL10D
35
PL10C
34
PL10B
33
PL10A
32
NC2
31
VCCIO2
37
VCCIO2
51
VCCIO2
66
PB4A
38
PB4B
39
CSSPIN/PB4C
40
PB4D
41
PB6A
42
PB6B
43
MCLK/CCLK/PB6C
44
SO/SPISO/PB6D
45
PB9C
47
PB9D
48
PCLKT2_0/PB9A
49
PCLKC2_0/PB9B
50
PB11D
54
PCLKT2_1/PB11A
55
PCLKC2_1/PB11B
56
PB11C
52
PB15A
57
PB15B
58
PB15C
59
PB15D
60
PB18A
61
PB18B
62
PB18C
65
PB18D
67
PB20A
68
PB20B
69
SN/PB20C
70
SI/SISPI/PB20D
71
NC3
63
100 R39 DNI
C27
0.01uF
J4
Header2x20
DNI
2
4
6
8
10
12
14
16
18
20
24
22
26
28
30
32
34
36
38
40 39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
1
3
5
7
C32
0.1uF
C25
0.1uF
C30
0.1uF
R33 DNI
100 R34 DNI
C29
0.1uF
100 R36 DNI
R29 DNI
R54
0
R26 1
R27 1
C34
0.1uF
C31
0.01uF
C33
0.1uF
100 R40 DNI
C26
0.1uF
100
100
100
100
Lattice MachXO2 1200ZE Breakout Board – FPGA
Thursday, April 21, 2011
Note:
1. The Pin Functions indicated in the schematic symbol U3 are for LCMXO2-1200ZE-1TG144C. For the Pin
Functions of the board with LCMXO2-7000HE-4TG144C, refer to the pinout file.
2. In the version of the board with LCMXO2-7000HE-4TG144C, the net name "VCCIO3" is also connected to Pin 7
(VCCIO5), and Pin 16 (VCCIO4).
3. Pin 7 of the version of the board with LCMXO2-7000HE-4TG144C, is VCCIO5.
4. Pin 16 of the version of the board with LCMXO2-7000HE-4TG144C, is VCCIO4.