C
REATING
C
USTOM
C
OMPONENTS
IN
L
ATTICE
M
ICO
S
YSTEM
:
Creating the Verilog Wrapper for VHDL Designs
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LatticeMico32 Hardware Developer User Guide
3. Import the VHDL source code into the project. During synthesis, turn off
I/O insertion by following these steps:
a. Select the File List tab in Diamond and double-click the name of the
currently active strategy, which is displayed in bold type.
b. In the Strategies dialog box, expand the Synthesis folder and select
the synthesis tool you will be using.
c. In the synthesis pane on the right, set Disable IO Insertion to
True
and
click
OK
.
d. In Diamond, select the Process tab , and double-click
Translate
Design
.
Diamond now generates the <
platform
>.ngo file.
4. Create a black-box declaration of the component in Verilog.
This declaration represents this component in any platform generated by
MSB that uses this component. It is combined with the .ngo file previously
created (that holds the actual functionality of the component) after
synthesis in the Translate Design process. If there are any bidirectional I/
Os in the custom VHDL component, you must declare them as black-box
pads. Lattice Semiconductor FPGAs only have tristate buffers in their I/O
cells. In a single-language implementation, the synthesis tool can
reconcile multiple tristate I/O requests to a single tristate buffer. In the
dual-language implementation, the Verilog wrapper has no visibility into
the VHDL .ngo black-box element, preventing any reconciliation of
multiple tristate buffers. The black-box pad declaration directs the
synthesis process not to create a second set of tristate buffers because
tristate buffers have already been created for these black-box ports.
Figure 45 is an example Verilog black-box definition of a VHDL custom
component illustrating the black_box_pad declaration in the Verilog black-
box definition for the VHDL custom component's inout port. This Verilog
black-box definition is the RTL input file for the custom component GUI.
5. Perform the user-defined component flow explained at the beginning of
this chapter to bring a user-defined Verilog component into MSB. The
Verilog component RTL file entry is the Verilog black-box file that you
created in step 4.
If there are tristate (bidirectional) I/Os in the custom VHDL component, you
must also add the black_box_pad_pin attribute of these ports to the VHDL
wrapper files’ component declaration section. The black_box_pad_pin
attribute is a synthesis directive that specifies pins on a user-defined black-
box component as I/O pads that are visible to the environment outside of the
black box. Because the I/O primitives are added to the tristate (bidirectional)
I/Os in the .ngo file, adding the black_box_pad_pin attribute to these I/Os
enables the top-level VHDL RTL code to recognize them.
Note
The Verilog module name must match the .ngo file name in order for Diamond to
correctly link the .ngo contents to the Verilog wrapper.
