ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3
6.2.5.
Dynamic Margin Control on DQSBUF
The ECP5 and ECP5-5G family includes dynamic margin control signals in the DQSBUF module allows you to dynamically
adjust the read or write side DQS delays generated in the DDRDLL.
Once the margin control mode is enabled by de-asserting WRLOADN (=1) or RDLOADN (=1), the DQSBUF’s phase shift
control to make a center aligned interface is no longer controlled by the DDRDLL component. It becomes your
responsibility to complete the margin control training to maximize the valid window and then continuously monitor the
DDRDLL delay code (DCNTL7~DCNTL0) and controls the DQSBUF delays accordingly using the WR/RDMOVE and
WR/RDDIRECTION signals to compensate the PVT variations.
6.2.6.
Read Data Clock Domain Transfer Using Input FIFO
Each IDDR module in the ECP5 and ECP5-5G device has a dedicated input FIFO to provide a safe clock domain transfer
from the DQS domain to the ECLK or SCLK domain. The input FIFO is 8-level deep with 3-bit write and read pointers. It
transfers the read data from the non-continuous DQS domain to the continuous ECLK. The FIFO is written by the DQS
strobe and read back by ECLK which has the identical frequency rate as DQS.
The input FIFO also performs the read leveling function. When each DQS strobe signal and its associated DQ data
signals arrive at slightly different time with others to the FPGA, the input FIFO allows the skewed read data to be
captured and transferred properly.
Each DQS group has one FIFO control in the DQSBUF block. It distributes the FIFO read/write pointers, WRPNTR [2:0]
and RDPNTR [2:0], to each memory IDDR module in the same DQS group. Safe domain crossing between ECLK and SCLK
is guaranteed by the ECP5 and ECP5-5G device hardware design.
6.2.7.
DDR Input and Output Registers (IDDR/ODDR)
ECP5 and ECP5-5G devices provide dedicated input DDR (IDDR) and output DDR (ODDR) functions supporting 4:1(X2)
gearing modes that are used to implement the DDR memory functions. These automatically handle the transfer of data
from ECLK domain to the SCLK (FPGA clock) domain.
6.3.
Memory Interface Implementation
The following sections explain the DDR2, DDR3/DDR3L, LPDDR2, LPDDR3 memory interfaces implementation using the
X2 gearing mode. ECP5 and ECP5-5G devices support these memory interfaces generation through the Clarity Designer
tool. Clarity Designer generates one module that includes the Read and Write side implementation shown below.
All of the memory interfaces use DQS clock, one ECLK and one SCLK to implement the read and write side operations.
ECLK must always be routed on the Edge Clock tree and SCLK on the primary clock tree.
6.3.1.
Read Implementation
The read side implementation is shown in
