ECP5 and ECP5-5G High-Speed I/O Interface
Technical Note
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FPGA-TN-02035-1.3
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3.7.
DLLDEL
DLLDEL provides phase shift on the receive side clocks to each ECLK. It functions similar to the DQSBUF, shifting the
clock input by delay set by the DDRDLL delay code, before the clock drives the clock tree. The DLLDEL element has the
ability to further adjust the delay from the delay set by the DDRDLL code, by using the MOVE and DIRECTION inputs
controlled by the user logic. The LOADN resets the delay back to the DDRDLL code.
3.8.
Input DDR (IDDR)
The input DDR function can be used in either 1x (2:1), 2x (4:1), or 7:1 gearing modes. In the 1x mode, the IDDR module
inputs a single DDR data input and SCLK (primary clock) and provides a 2-bit wide data synchronized to the SCLK
(primary clock) to the FPGA fabric.
The 2x gearing is used for interfaces with data rate higher than 400Mbps which would require higher than 200 MHz
system clock. There the IDDR element inputs a single DDR data input and DQS clock (for DDR memory interface) or
ECLK (for all other high-speed interfaces) and provides a 4-bit wide parallel data synchronized to SCLK (primary clock) to
the FPGA fabric.
In the 7:1 mode, mostly used in video applications required 7:1 interface, the IDDR element inputs a single DDR data
input and ECLK and output a 7-bit wide parallel data synchronized to SCLK (primary clock) to the FPGA fabric.
3.9.
Output DDR (ODDR)
The output DDR function can also be supported in 1x (2:1), 2x (4:1), or 7:1 gearing modes. In the 1x mode, the ODDR
element receives 2-bit wide data from the FPGA fabric and generates a single DDR data output and Clock output.
Similar to input interfaces the 2x gearing is used for data rate higher than 400 Mbps which would require higher than
200 MHz system clock. Here the ODDR element receives 4-bit wide data from the FPGA fabric and generates a single
DDR data output and clock output. The 2x element uses high-speed edge clock (ECLK) to clock the data out for generic
high-speed interfaces and DQS clock for DDR memory interfaces.
In 7:1 mode, the ODDR element receives 7-bit wide data from FPGA fabric and generates a single DDR data output and
Clock output. The 7:1 element sends out data using high-speed edge clock.
3.10.
Edge Clock Dividers (CLKDIV)
Clock dividers are provided to create the divided down clocks used with the I/O Mux/DeMux gearing logic (SCLK inputs
to the DDR) and drives to the Primary Clock routing to the fabric. There are two clock dividers on each side of the
device.
3.11.
Input/Output DELAY
There are two different types of input/output data delay available. Both DELAYF and DELAYG provide a fixed value of
delay to compensate for clock injection delay. The DELAYF element also allows you to set the delay value using 128
steps of delay. Each delay step generates ~25 ps of delay. In DELAYF, you can overwrite the DELAY setting dynamically
using the MOVE and DIRECTION control inputs. The LOADN resets the delay back to the default value.
