CrossLink Programming and Configuration Usage Guide
Technical Note
© 2015-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at
. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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FPGA-TN-02014-1.2
5.
Configuration Modes
CrossLink provides multiple options for loading the configuration SRAM from a non-volatile memory. The previous
section describes the physical interface necessary to interact with the CrossLink Configuration Logic. This section
describes the functionality of each of the different configuration modes. Descriptions of important settings required in
the Diamond Spreadsheet View are also discussed. See the
section on page 9 for details on the default
configuration behavior of the device.
5.1.
SDM Mode
SDM (Self-Download Mode) is the primary configuration method for CrossLink. The advantages of SDM include:
Speed
: CrossLink is ready to run in a few milliseconds depending on the density of the device.
Security
: The configuration data is never seen outside the device during the load to SRAM. You can prevent the
internal memory from being read.
Reduced cost
: There is no need to purchase a PROM specifically reserved for programming CrossLink.
Reduced board space
: Elimination of an external PROM allows your board to be smaller.
CrossLink retrieves the configuration data from the internal NVCM when it is using Self Download Mode. SDM is
triggered when power is applied, a REFRESH command is received, or by asserting the CRESETB pin from HIGH to LOW.
5.2.
Master SPI Configuration Mode
Master SPI (MSPI) configuration mode is the only other self-controlled configuration mode available to CrossLink.
Lattice recommends having a secondary configuration port available that is active when CrossLink is in Feature Row
HW Default Mode state (that is, blank). The secondary port allows you to recover CrossLink in the event of a
programming error.
For CrossLink to operate correctly using the MSPI configuration mode, ensure that:
The POR of the SPI Flash device is lower than the POR of CrossLink or the SPI Flash is powered first.
SPI Flash Fmax is greater than CrossLink MCK Fmax.
Board routing requirements are checked to ensure CrossLink setup and hold time parameters are met. Refer to the
CrossLink Family Data Sheet (FPGA-DS-02007)
for detailed setup and hold time information.
Table 5.1. Master SPI Configuration Port Pins
Pin Name
Function
MCK
Clock output from the CrossLink Configuration Logic and Master SPI controller. Connect MLK to the SCLK input
of the Slave SPI device.
MOSI
Serial Data output from CrossLink to the slave SPI SI input.
MISO
Serial Data input to the CrossLink Configuration Logic from the slave SPI SO output.
CSN
Chip select output from the CrossLink Configuration Logic to the slave SPI Flash holding configuration data for
CrossLink.
provides information about the amount of memory needed for CrossLink configuration data by device
density. Select an SPI Flash that accepts 03 hex Read Opcodes. CrossLink is only able to use the 03 hex Read Opcode.
CrossLink begins retrieving configuration data from the SPI Flash when power is applied, a REFRESH command is
received, or the CRESETB pin’s LOW to HIGH transition which puts the FPGA into Master SPI configuration mode. The
MCK/SPI_SCK I/O takes on the Master Clock (MCK) function, and begins driving a nominal 2 MHz clock to the SPI Flash’s
SCLK input. CSSPIN is asserted LOW, commands are transmitted to the PROM over the MOSI output, and data is read
from the PROM on the MISO input pin. When all of the configuration data is retrieved from the PROM, the CSSPIN pin
is deasserted and the MSPI output pins are tri-stated.
The MCK frequency always starts downloading the configuration data at the nominal 2 MHz frequency. The
MCCLK_FREQ parameter, accessed using Spreadsheet View, can be used to increase the configuration frequency.
The configuration data in the PROM has some padding bits, and then the data altering the MCK base frequency is read.
CrossLink reads the remaining configuration data bytes using the new MCK frequency.