LAPIS Semiconductor ML7406, Hardware Design Manual, Page: 12 / 24

ML7406 Family LSIs Hardware Design Manual
FEXL7406DG-01
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3. PLL loop filter
Figure 3.1 shows a configuration example of the PLL loop filter circuit. To satisfy phase noise feature, the
recommend values are showed in Figure 4.1.
It is recommended to select the components with flat temperature characteristics and temperature coefficient is
managed. Capacitors, do not select high dielectric type and semiconductor type, so there is low accuracy and
non-linear temperature characteristics.
In order to prevent noise, the loop filter components (C2, R3 and C3) should be placed as close to the LP (#26)
pin as possible, recommends within 5 mm. Do not trace signal lines that become a noise source like a reference
clock line, around the loop filter.
Figure 3.1 PLL loop filter circuit configurations
LP(#26)
C2
10pF
R3
13kΩ
C3
3300pF