Lake Shore Cryotronics F71, User Manual

Page: 62 / 97

54 c
HAPTER
4: Computer Interface Operation
F71/F41 Teslameter
4.3.1.6.3 Clearing Registers
The methods to clear each register are detailed in the table below.
4.3.2 Register Details 4.3.2.1 Status Byte Register
The summary messages from the event registers and the output buffer set or clear the
summary bits of the status byte register (FIGURE 4-2). These summary bits are not
latched. Clearing an event register will clear the corresponding summary bit in the
status byte register. Reading all messages in the output buffer, including any pending
queries, will clear the message available bit. Reading all errors out of the queue will
clear the error available bit. The bits of the status byte register are described as fol-
lows:
D
Operation Summary (OSB), Bit (7): this bit is set when an enabled operation event has
occurred.
D
Master Summary Status (MSS), Bit (6): this bit is set when a summary bit and the
summary bit’s corresponding enable bit in the service request enable register are
set. A *STB? will read the status of the MSS bit (along with all of the summary
bits), but also will not clear it. To clear the MSS bit, either clear the event register
that set the summary bit or disable the summary bit in the service request Enable
register.
In addition, in other instruments with a GPIB interface, this bit is also defined as
the Request Service (RQS) bit. In this case, when the RQS/MSS bit would be set,
the service request hardware line would go high, indicating to the controller on
the bus to query the status byte. Since the F71/F41 teslameter does not have a
GPIB interface, this bit is strictly referred to as the MSS bit.
D
Summary (ESB), Bit (5): this bit is set when an enabled standard event has occurred.
D
Message Available (MAV), Bit (4): this bit is set when a message is available in the out-
put buffer.
D
Questionable Summary (QSB), Bit (3): this bit is set when an enabled questionable
event has occurred.
Register Method Example
Condition registers None: registers are not latched —
Event registers:
Standard event status register
Operation event register
Query the event register
*ESR?
(clears standard event status register)
Send *CLS
*CLS
(clears both registers)
Power on instrument —
Enable registers:
Standard event status enable register
Operation event enable register
Service request enable register
Questionable event enable register Write 0 to the enable register
*ESE 0
(clears standard event status enable
register)
Power on instrument —
Status byte
There are no commands that directly clear the status byte as the
bits are non-latching; to clear individual summary bits clear the
event register that corresponds to the summary bit—sending *CLS
will clear all event registers which in turn clears the status byte
If bit 5 (ESB) of the status byte is set,
send *ESR? to read the standard event
status register and bit 5 will clear
Power on instrument —
TABLE 4-2 Register clear methods