WB50NBT
Hardware Integration Guide
Embedded Wireless Solutions Support Center:
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www.lairdtech.com/wi-fi
10
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Power on Sequence
Notes:
Apply the 3.3 V (backup and system) at the same time.
The CPU implements the internal POR (Power-On-Reset) and guarantees that the power sources reach
their target values prior to the release of POR.
DC Electrical Characteristics (3.3 V signal level)
I/O
Indicates whether the signal is input or output state.
PU/PD
Indicates whether Pull-Up, Pull-Down, or nothing is enabled.
ST
Indicates if Schmitt Trigger is enabled.
TR
Tri-state
GPIO [1-6]
PIO, I, PU, ST
LED [0-2]
PIO, I, PU, ST
STAT_0; STAT_1
PIO, I, PU, ST
SHDN
O
NRST
I, PU, ST
BINT
I, PU, ST
WKUP
I,PU, ST
DDM; DDP; HDMA; HDPA; HDMB; HDPB
O, PD
E_TXEN; E_TX [0-1]; E_RXER; E_RX [0-1]; E_MDC;
PIO, I, PU, ST
E_MDIO; E_CRSDV; E_REFCK; E_RST_L; E_INT
TBD
BT_PCM_OUT; BT_PCM_IN; BT_PCM_SYNC; BT_PCM_CLK
TBD
XPABIAS50; XPABIAS51; XPABIAS20; XPABIAS21
TBD
AR6004_GPIO38
TBD
LTE_ACTIVE
TBD
LTE_FRAME_SYNC
TBD
WCN_PRIORITY
TBD
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low-Level Voltage
-0.3
-
0.8
V
V
IH
Input High-Level Voltage
2.0
-
3.6
V
V
OL
Output Low-Level Voltage
-
-
0.4
V
V
OH
Output High-Level Voltage
2.9
-
-
V
V
HYS
Schmitt trigger Hysteresis
0.34
-
-
V
R
PULLUP
Pull-up/Pull-down Resistance
45
100
130
K
Ω
I
O
Output Current
-
-
8
mA
