PT5040 Operation Manual Chapter 9 Handler interface
Chapter 9 Handler interface
Basic
information
The handler interface employs a 9-pin DB connector. Pin sequence is as follow.
5 4 3 2 1
9 8 7 6
(side view)
The signal definitions for each pin are described as follows:
Note: The / (back slash) in the signal name means that the signal is asserted when low
level
PIN
EXGND: Common for external voltage source EXV.
When PT50xx series uses the internal voltage as the power supply for handler
interface, PT50xx series‟ circuit common will be connected to EXTEND.
PIN
/EOC: End of conversion.
/EOC signal is asserted when the A/D conversion is completed and PT50xx series
is ready for the next DUT to be connected to the test terminals. The measurement
data, however, is not valid until BUSY is asserted to low.
PIN
BUSY: PT50xx series is in the test state. When calculation, comparison and display are
all completed, this signal is asserted to low.
PIN
/PASS: Pass signal output.
PIN
/FAIL: Fail signal output.
PIN
EXV: External DC voltage
DC voltage supply pins for DC isolated collector outputs, /EOC, /START, /STOP,
/PASS, /FAIL, /EOM. The setting of internal jumpers must be changed when
using the internal voltage supply.
PIN
/START: External trigger signal.
PT50xx series is triggered bon the rising edge of a pulse applied to this pin when
the trigger mode is set to EXT mode.
PIN
/STOP: External stop signal
Test is interrupted on the rising edge of a pulse applied to this pin.
PIN
VCC: Internal voltage source supply (+5V)
Internal source is not recommended for user to use. Make sure the current is
lower than 0.1 A and keep the signal line be away form interference source
9-2
