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User’s Guide
KDS AC Specifications
All timings specified below are measured at 2.5 Volts
Output.
Measured at the KDS Output connector, the minimum duration of
KDS Clock Low or High is 32ns. The total time difference from any KDS Clock
output transition to KDS Sync output transition, or from any KDS Clock
output transition to KDS Data output transition, is 12ns maximum. This figure
is the sum of output-to-output skew, plus jitter introduced by the device that
generates the three signals which contributes 2ns (max.), the AM26LS31 which
contributes 6ns (max.), the EMI common mode choke and capacitors which
contribute 1ns (max.), and the combined circuit Low-to-High and High-to-
Low asymmetry which is 3ns (max.).
Cable.
Jitter and skew contributed by the cable consisting of cable reflections,
nonlinearity, and delay mismatch for up to 15 meters of Belden 9806 cable is
estimated to be 3ns, maximum.
Input.
A single AM26LS32B is used to receive the three signals. The
AM26LS32B is an improved version of the 26LS32 that features guaranteed
minimum hysteresis and skew, plus a much improved output driver.
Measured at the output of the receiver, the time difference between any KDS
signal transition to any other signal transition should be no more than 22ns,
maximum. This figure is the sum of output to output skew, plus jitter
introduced by the output circuit which is 12ns (max.), the cable which is 3ns
(max.), the receiver which is 4ns (max.), the EMI common mode choke and
capacitors which contribute 1ns (max.), and the asymmetry of the receiving
circuit which is 2ns (max.).
Receiving Logic.
The rising edge of KDS Clock is used to detect KDS Sync and
latch KDS Data. With 22ns of total interface skew, jitter, and asymmetry at the
output of the receiver and a 32ns minimum KDS Clock input High and Low
time, the resulting KDS Sync and KDS Data setup and hold time with respect
to the rising edge of KDS Clock is 10ns, minimum. Typical interface skew,
jitter, and asymmetry measured at the output of the DMTi KDS receiver is 3ns,
much lower than the maximum calculated value. If one pays close attention to
minimizing skew in the design, PC board layout, and cable of the KDS inter-
face, the result will be more setup and hold margin at the receiver.