SMARC-sAL28 User Guide. Rev. 1.0
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8.3.
PCI
In case if the optimization/customization of the BSP kernel, it is necessary to make sure that
CONFIG_PCIE_DW_PLAT is still enabled in kernel config. Otherwise the PCIe controller won't be initialized properly
and particular PCIe Gen2 devices won't be enumerated and detected automatically during boot.
8.4.
I2C Buses
I2C_PM and I2C_GP buses on SMARC carrier are mapped to i2c-1 and i2c-2 devices accordingly:
# i2cdetect -l
i2c-1 i2c 2030000.i2c I2C adapter
i2c-2 i2c 2040000.i2c I2C adapter
These devices can be accessed using a standard dev-interface API:
https://elixir.bootlin.com/linux/v4.14/source/Documentation/i2c/dev-interface
8.5.
SPI Buses
SPI0 on SMARC connector is an “ordinary” SPI bus governed by Freescale DSPI controller/driver. To make this bus
available in KEAPI, an spidev driver is bound in sl28.dts device tree file:
&dspi2 {
bus-num = <2>;
status = “okay”;
dspidev@0 {
compatible = “spidev”;
reg = <0>;
spi-max-frequency = <50000000>;
};
};
As a result, the bus can be accessed via standard dev-interface as /dev/spidev2:
https://elixir.bootlin.com/linux/v4.14/source/Documentation/spi/spidev
ESPI on SMARC connector is handled by Flex SPI controller/driver. This controller is optimized for SPI-NOR flash
reading usecase and is not suitable for generic SPI transfers of arbitrary length. So devices other than flash are not
supported.
The BSP provides an MTD interface for SPI-NOR flash chips connected to ESPI bus. User needs to adjust DTS file and
describe connected chips in fspi node in the device tree. Here's example DTS snippet for Winbond W25Q128FW chip:
&fspi {
flash1: w25q128fw@1 {
# address-cells = <1>;
# size-cells = <1>;
compatible = “jedec,spi-nor”;
m25p,fast-read;
spi-max-frequency = <30000000>;
reg = <1>;
/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <4>; /* 4 SPI Rx lines */
spi-tx-bus-width = <4>; /* 4 SPI Tx line */
status = “okay”;
};
};
reg property should correspond to cs: 0 for ESPI_CS0#, 1 for ESPI_CS1#
The BSP provides a read-only access to on-module SPI flash with U-Boot boot loader.
The BSP provides a read-only access to on-module SPI flash with U-Boot boot loader, and which is located at ESPI
bus at CS0, via MTD interface:
mtd0: 00010000 00001000 "rcw"
mtd1: 000f0000 00001000 "failsafe bootloader"
mtd2: 00040000 00001000 "failsafe DP firmware"
Summary of Contents for SMARC-sAL28
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