Hot Swap
CP690HS
Page 5 - 10
ID 20955, Rev. 05
P R E L I M I N A R Y
5.2.6.3
GPIO Output Data Register - Offset 65h
This section describes the GPIO output data register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = xx0xb
Table 5-5:
GPIO Output Data Register - Offset 65h
Dword BIT
NAME
R/W
DESCRIPTION
11:8
GPIO output
enable
write-1-to-clear
R/W1TC
The gpio<3:0> pin output data
write-1-to-clear. Writing 1 to any of these bits drives the corre-
sponding bit low on the gpio<3:0> bus if it is programmed as
bi-directional. Data is driven on the PCI clock cycle following
completion of the
configuration write to this register. Bit positions corresponding to
gpio pins that are programmed as input only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
Reset value: 0.
15:12
GPIO output
enable
write-1-to-set
R/W1TS
The gpio<3:0> pin output data
write-1- to-set. Writing 1 to any of these bits drives the corre-
sponding bit high on the gpio<3:0> bus if it is programmed as
bi-directional. Data is driven on the PCI clock cycle following
completion of the
configuration write to this register. Bit positions corresponding to
gpio pins that are programmed as input only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
Reset value: 0.
Summary of Contents for CP690HS
Page 17: ...CP690HS Introduction ID 20955 Rev 05 Page 1 1 Introduction Chapter 1 1 P R E L I M I N A R Y...
Page 39: ...Installation Chapter 1 3 ID 20955 Rev 05 Page 3 1 CP690HS Installation P R E L I M I N A R Y...
Page 47: ...Configuration ID 20955 Rev 05 Page 4 1 CP690HS Configuration P R E L I M I N A R Y Chapter 1 4...
Page 51: ...Hot Swap ID 20955 Rev 05 Page 5 1 CP690HS Hot Swap P R E L I M I N A R Y Chapter 1 5...
Page 73: ...CP RIO6 90 ID 20955 Rev 05 Page A 1 CP690HS CP RIO6 90 P R E L I M I N A R Y Appendix A...
