CP6006-SA – User Guide, Rev. 0.5 Preliminary
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2.7.11.
High-Speed Serial Rear I/O Interconnection
The high-speed serial rear I/O interconnection has been designed to meet the PICMG 2.20 R1.0 standard. In addition,
Kontron has made minor improvements to ensure maximum signal integrity, such as:
upgraded high-speed ZDplus connector mechanically compliant with the PICMG 2.20 providing better shielding
to support up to 15 GHz signal frequency
high-speed interconnection supporting 10GBASE-KR/40GBASE-KR4, one x8 PCI Express 3.0 port operating at 8
GT/s and two SATA 6 Gb/s ports
The PICMG 2.20 configuration allows coexistence with PICMG 2.16 fabrics.
Table 28: High-Speed Serial Rear I/O Interconnection Port Mapping
CON
POS
PICMG 2.20
PORT DEFINITION
CP6006X-SA
J41
1
AUX
PCIe Control
PCIe Control
2
PORT 1
10GBASE-KR/
40GBASE-KR4 Port 1
10GBE1
3
PORT 2
--
4
PORT 3
--
5
PORT 4
--
6
PORT 5
10GBASE-KR/
40GBASE-KR4 Port 2
10GBE2
7
PORT 6
--
8
PORT 7
--
9
PORT 8
--
10
PORT 9
SATA 6 Gb/s Port 1
SATA Port 4
J4
11
PORT 10
SATA 6 Gb/s Port 2
SATA Port 5
12
PORT 11
1 x8 PCIe
Gen 3
1 x8 PCIe
Gen 3
13
PORT 12
14
PORT 13
15
PORT 14
16
PORT 15
17
PORT 16
18
PORT 17
19
PORT 18
20
CLOCK
PCIe Reference Clock
PCIe Reference Clock
