Configuration
CP3003-SA
Page 4 - 4
ID 1052-6929, Rev. 3.0
D R A F T — F O R I N T E R N A L U S E O N L Y
4.1.1
I/O Address Map
The following table indicates the CP3003-SA-specific registers.
Table 4-2: I/O Address Map
ADDRESS
DEVICE
0x080
uEFI BIOS POST Code Low Byte Register (POSTL)
0x081
uEFI BIOS POST Code High Byte Register (POSTH)
0x082 - 0x083
Reserved
0x084
Debug Low Byte Register (DBGL)
0x085
Debug High Byte Register (DBGH)
0x280
Status Register 0 (STAT0)
0x281
Status Register 1 (STAT1)
0x282
Control Register 0 (CTRL0)
0x283
Control Register 1 (CTRL1)
0x284
Device Protection Register (DPROT)
0x285
Reset Status Register (RSTAT)
0x286
Board Interrupt Configuration Register (BICFG)
0x287
Status Register 2 (STAT2)
0x288
Board ID High Byte Register (BIDH)
0x289
Board and PLD Revision Register (BREV)
0x28A
Geographic Addressing Register (GEOAD)
0x28B
Reserved
0x28C
Watchdog Timer Control Register (WTIM)
0x28D
Board ID Low Byte Register (BIDL)
0x28E - 0x28F
Reserved
0x290
LED Configuration Register (LCFG)
0x291
LED Control Register (LCTRL)
0x292
General Purpose Output Register (GPOUT)
0x293
General Purpose Input Register (GPIN)
0x294 - 0x29F
Reserved
