Keysight M9502A, User Manual

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Keysight M9502A/M9505A AXIe Chassis User Guide 103
Chassis Backplane Connections For Module Developers
Zone 1 Pin Assignments
The Zone 1 pin assignments and circuit definitions for backplane connector J10
and module connector P10 are listed below:
Power Circuit Contacts for J10/P10
Legacy ATCA Test Circuit Pins for J10/P10
Hardware Management Circuit Contacts for J10/P10
Contact
Number ATCA
Designation Description
25 SHELF_GND Connection to Shelf Ground and safety ground
26 LOGIC_GND Ground reference and return for Front Board-to-Front Board
logic signals
27 ENABLE_B Short pin for power sequencing, Feed B, tied to VRTN_B on backplanes
28 VRTN_A –48 v return, Feed A
29 VRTN_A –48 v return, Feed B
30 EARLY_A –48 v input, Feed A pre-charge
31 EARLY_B –48 v input, Feed B pre-charge
32 ENABLE_A Short pin for power sequencing, Feed A, tied to VRTN_A on backplanes
33 –48V_A –48 v input, Feed A, uses ENABLE_A to enable converters
34 –48V_B –48 v input, Feed B, uses ENABLE_B to enable converters
Contact
Number ATCA
Designation Description
17 MT1_TIP
These backplane J10 contacts will physically accept pins from ATCA
modules, but do not provide ATCA metallic test and ringing generator bus
circuits.
18 MT2_TIP
19 –RING_A
20 –RING_B
21 MT1_RING
22 MT2_RING
23 RRTN_A
24 RRTN_B
Contact
Number ATCA
Designation Description
1-4 Reserved, do not connect
5 HA0 Hardware address bit 0
6 HA1 Hardware address bit 1
7 HA2 Hardware address bit 2
8 HA3 Hardware address bit 3
9 HA4 Hardware address bit 4
10 HA5 Hardware address bit 5
11 HA6 Hardware address bit 6
12 HA7/P Hardware address bit 7 (odd parity bit)
13 SCL_A IPMB clock, Port A
14 SDA_A IPMB data, Port A
15 SCL_B IPMB clock, Port B
16 SDA_B IPMB data, Port B