Keysight 33210A, User Manual

Page: 315 / 351

313
Chapter 7 Tutorial
Direct Digital Synthesis
4
7
Phase Accumulator Circuitry
The 33210A uses a 64-bit phase accumulator which yields 2
-64
x 50 MHz or
2.7 picohertz frequency resolution internally. Note that only the 13 or 14
most-significant bits of the Phase Register are used to address waveform
memory. Therefore, when synthesizing low frequencies (less than 3.05
kHz for a typical, 16K point standard waveform), the address will not
change in every clock cycle. However, at higher frequencies (greater than
3.05 kHz), the address will change by more than one location during each
clock cycle and some points will be skipped. If too many points are
skipped, a phenomenon known as “aliasing” will occur and the waveform
output will become somewhat distorted.
50 MHz
Waveform
Phase
Adder
64 Bits
Phase
Register
Register (PIR)
64 Bits
MSBs
(13 or 14 bits)
Memory
Address
Increment
64 Bits
The Nyquist Sampling Theorem states that in order to prevent aliasing,
the highest frequency component of the desired output waveform must
be
less than half
of the sampling frequency. The Keysight 33210A
samples at 50 MHz, so Nyquist limits the highest frequency component
to 25 MHz while the anti-alias filtering limits the highest frequency
component to less than this.
33210A users guide.book Page 313 Wednesday, July 16, 2008 11:16 AM