Keysight Technologies N8241A, User Manual

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86 Chapter 3
Theory of Operation
Multiple Module Synchronization
Multiple Module Synchronization
Within each AWG, the two channels are synchronized by design. Some systems,
such as phased array radar, require more than two synchronized channels. The AWG
is designed to support the synchronization of up to 16 channels through the use of
eight AWGs. Synchronization of multiple AWGs can be achieved using either the
internal clock or an external clock.
Synchronization Using an Internal Clock
In synchronizing multiple modules using the internal clock, one unit is designated as
the Master and the other units are designated as Slave units. The Master unit sources
the following signals: Sample clock, SYNC clock, and the Sync Marker. These
signals are all split and fed to each of the synchronized modules (the Master as well
as the Slaves).The internal sample clock is at 1.25 GHz. The sample clock provides
the final retiming of the analog output from each AWG. Any skew in the sample
clock cable delays between the multiple modules will result in the same skew in the
analog outputs.
Typically, the sample clock signal is split with a matched passive splitter and the
cable lengths are matched to better than 5 mm. The resulting skew is small and
repeatable. If desired, the skew can be measured and calibrated (along with any
phase shifts in cables on the AWG outputs) by adding fixed delay offsets to the
waveforms.
The SYNC clock is used internal to the AWG to clock the internal data generator
and to clock in the synchronous triggers. When using the internal clock, the SYNC
clock has a frequency of 1/8th the sample clock rate (156.25 MHz). When
synchronizing multiple units, the SYNC clock output must be enabled in software
(in the Master) and the external SYNC clock input selected in all the modules. The
SYNC clock signal is split passively and distributed with low skew. The SYNC
clock output level and the input sensitivity support up to a 1 to 8 split (fan-out) using
matched 50 Ohm splitters (6 dB loss per 1 to 2 splitter). There is a specific SYNC
cable length that is required as a function of the sample clock frequency. Several
different lengths can be used, provided they are integer multiples of one half of a
SYNC clock period.