8
Keysight M9506A AXIe Chassis Startup Guide
Introduction
M9506A System Block Diagram (Graphic)
NOTES:
PCIe and
LAN connectivity:
$
If
the chassis
PCIe interface is
connected
and
the chassis
LAN
interface isn’t connected,
the Intel
NIC provides
a means for
th
e
PC to
access
the LAN
Switch
–
this provides
PC
access
to the
Shelf
Manager
as well
as access
to the
Gb
Ethernet
connections
to each slot.
%
While the
Intel NIC allows
the
host
PC
to
use the
PCIe
interface to
access
the LAN
Switch
(and
the
devices
connected
to
the LAN
Switch), the
reverse
does not
apply --
the
PC
cannot
use the
LAN interface
and
the Intel NIC
to
access
the slot
PCIe
x16
interfaces.
PCIe Generation
(Gen)
1 peak
speed
is 2.5 G
E
/s per
lane.
PCIe
Gen
2 peak
speed is
5.0
G
E
/s per
lane.
PCIe
Gen
3 peak
speed is
8.0
G
E
/s per lane.
Taking
into account
encoding
and
other overhead,
typical
Gen
3 performances
in
G
E
/s are as
follows
for
x8 and
x16:
PCIe
Swit
ch
Site LAN
hub,
router, or
switch
PC
Ie
Adapter
Host PC
PC
Ie
cable
(G
e
n
3
, x8
)
Chassis LAN
interface
ESM PCIe
interface
IM
PO
RTANT:
PCIe is
logically
an extension
of the
host
PC backplane.
If the
PCIe interface
is
used
to connect to the chassis,
the chassis
Intel I210
NIC
will appear to Windows as
if
it
is
installed
directly in
the PC.
Windows 7
an
d Windows 10
provide
the necessary
Intel NIC
driver.
If
you’re connected
to the chassis
using
only
the LAN
interface,
the NIC
will not be
visible
to
the
Host Controller
PC and the above
dialog
won’t
be displayed.
Keysight Connection
Expert
Keysight
Connec
tion
Expert
displays c
o
nnec
ti
on
information separately
for
the
chassis
and for
each module
inst
alled in
th
e
chassis.
Keysight M9506A AXIe Chassis
System
LAN
Swit
ch
Keysight M9506A
AXIe
Chassis
Monitors/
contro
ls
fan
speeds
Monitors te
mpe
rature
sensors
Monitors module
sensors
Provides Web
Interface
Shelf
Mana
g
e
r
IPMB –
Intelligent
Platform Management Bus
P
C
Ie
x
16 (
G
en
3)
to e
a
ch
s
lot
Gb Et
hernet
to e
a
ch
s
lot
Synchronization
and Triggering
^ůŽƚ
ϭ
^ůŽƚ
Ϯ
^ůŽƚ
ϯ
^ůŽƚ
ϰ
^ůŽƚ
ϱ
Parallel and
star
trigger lines
AXIe
Chassis
Soft Front Panel (SFP)
The SFPs
use
PC
Ie,
LA
N,
or Thunderbolt 3
M
9047,
M
9048,
M
9049 P
C
Ie
De
sktop Adapte
r
(x8
)
Th
e
PC
Ie
x1
6
conne
ctions
to e
a
ch
slot can only
be
acce
ss
e
d
from
the c
hassis
PCI
e
int
erfac
e
. However, t
he Gb Et
hernet
conne
ctions
to
e
a
ch
slot
can
be
acce
ss
e
d
fr
om both
th
e
PC
Ie
interface (through
the
Intel NIC
and LAN
Switch) and through
the chassis
LAN interface.
Intel I210 Net
wo
rk
Interface Card
T
h
e s
lo
t
PC
Ie
inter
fa
ces
canno
t be
accessed
from
t
h
e
chassis L
A
N
interf
ace.
In performing the
Initialize()
c
a
ll
for
either
driver, the applic
ation
program
specifies
a
VISA resource
name.
If only PCIe
is connected,
the resource name
may
appear
like:
“T
CP
IP0
::
169
.2
54.
1.
0:
:50
25
::S
OC
KET
”
where 169.254.1.0
is an
example private IP address. If
only LA
N
is
connected, the
reso
urce
name may
appear like:
“TCPIP0::1
92
.1
68
.5
.2
::
50
25
::
SO
CK
ET
”
where 192.168.5.2
is an
example DHC
P-assigned
IP
address.
If
both
LAN
and
PCIe
are connected, the
LA
N VISA resource
name is
used.
Application program
IVI-C
driver
IVI .NET
driver
LAN
CAUTIO
N:
Do not attach
a
LAN
cable
after
communications
has
been established
over
the PCIe
cable. Doing
this
will
disrupt PCIe communications,
and will
not provide
LAN
communications
–
the chassis
will become
inaccessible and rebootin
g
of the
PC will be required
to restore communications.
If you
need both
LAN
an
d
PCIe communications,
connect both
cables
prior
to powering-up
the
chassis.
Chassis
Firmware
Modules may
connect
to
the
PCIe
x16 interface and/or the Gb
Et
hernet
int
erfac
e
.
Refer t
o
your
module documentation
for
information on the
interface(s)
it
uses.
ESM Thunderbolt
Inte
rface
Chassis Web
Interface
The Web Interfac
e uses
PC
Ie,
LAN,
or Thunderbolt 3.
Thunderbolt Interface
A
X
Ie
Chassis Monitor
SFP
A
X
Ie
Chassis Trigger
SFP
x8:
8 G
E
/s
x16:
16 G
E
/s
3.
The PCIe
Switch
internal
buffering
allows
the chassis
to
communicate
to
the
host
PC
at
16
G
E
/s
and distributes this bandwidth
across
all 5
slots.
