Keysight Technologies D9020DDRC, Manual, Page: 69 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 53
Measurement Clock Tests 3
Absolute Clock Period - tCK(abs) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement as well as the Falling Edge Measurement.
tCK(abs) is absolute clock period within 202 consecutive cycle window. The tCK(abs) Rising Edge
Measurement measures the period from the rising edge of a cycle to the next rising edge within the
waveform window. The tCK(abs) Falling Edge Measurements measures from the falling edge to the
falling edge.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Table 103 in the JESD209-2B .
Pass Condition
The tCK(abs) measurement value should be within the conformance limits as specified in the JEDEC
specification.
Measurement Algorithm
Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202.
1 Find the maximum period value for period 1-202.
2 Find the minimum period value for period 1-202.
3 Check these two results for the worst case values.
4 Compare the test result against the compliance test limit.
Table 26 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Absolute Clock
Period
t
CK
(abs) min t
CK
(avg),min + t
JIT
(per),min ps