Keysight Technologies D9020DDRC, Manual

Page: 67 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 51
Measurement Clock Tests 3
Average Clock Period - tCK(avg) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement as well as the Falling Edge Measurement.
tCK(avg) is average clock period within 200 consecutive cycle window. The tCK(avg) Rising Edge
Measurement measures the period from the rising edge of a cycle to the next rising edge within the
waveform window. The tCK(avg) Falling Edge Measurements measures from the falling edge to the
falling edge.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Table 42 - Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the JEDEC
Standard JESD79-2E, Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 ,
and Table 103 in the JESD209-2B.
Table 23 Timing Parameters by Speed Grade (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
Average clock period tCK(avg) 3000 8000 2500 8000 ps 35,36
Table 24 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
Average clock period tCK(avg) 1875 7500 ps 30,31
Table 25 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Average clock
Period
t
CK
(avg),
Min 1.875 2.15 2.5 3 3.75 4.3 5 6 7.5 10
ns
Max 100