Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 49
Measurement Clock Tests 3
Half Period Jitter - tJIT(duty) - Test Method of Implementation
The Half Period Jitter tJIT(duty) can be divided into tJIT(CH) Jitter Average HIGH and tJIT(LH) Jitter
Average Low. The tJIT(CH) Jitter Average HIGH Measurement measures between a positive pulse
width of a cycle in the waveform, and the average positive pulse width of all cycles in a 200
consecutive cycle window. tJIT(LH) Jitter Average Low Measurement measures between a negative
pulse width of a cycle in the waveform and the average negative pulse width of all cycles in a 200
consecutive cycle window.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Specific Note 35 in the JEDEC Standard JESD79-2E, Specific Note 30 in the JESD208 , and
Table 103 in the JESD209-2B.
Table 20 Specific Note 35
Parameter Symbol DDR2-667 DDR2-800 Units Notes
Min Max Min Max
Duty cycle jitter tJIT(duty) -125 125 -100 100 ps 35
Table 21 Specific Note 30
Parameter Symbol DDR2-1066 Units Notes
Min Max
Duty cycle jitter tJIT(duty) -75 75 ps 30
Table 22 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Duty cycle jitter
(with allowed
jitter)
t
JIT
(duty),
allowed
Min min((t
CH
(abs),min - t
CH
(avg),min), (t
CL
(abs),min - t
CL
(avg),min)) * t
CK
(avg)
t
CK
(avg)
Max max((t
CH
(abs),max - t
CH
(avg),max), (t
CL
(abs),max - t
CL
(avg),max)) * t
CK
(avg)