Keysight Technologies D9020DDRC, Manual

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3 Measurement Clock Tests
38 DDR2(+LP) Compliance Testing Methods of Implementation
Cumulative Error - tERR(n per) - Test Method of Implementation
This Cumulative Error (across “n” cycles) test is applicable to the Rising Edge Measurement as well
as the Falling Edge Measurement. The purpose of this test is to measure the difference between a
measured clock period and the average clock period across multiple cycles of the clock. Supported
measurements include multiple cycle windows with values of "n" (for "n" cycle) where n>5 but less
than 50.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Table 8 Specific Note 35
Parameter Symbol DDR2-667 DDR2-800 Units Notes
min max min max
Cumulative error across 2 cycles tERR(2per) -175 175 -150 150 ps 35
Cumulative error across 3 cycles tERR(3per) -225 225 -175 175 ps 35
Cumulative error across 4 cycles tERR(4per) -250 250 -200 200 ps 35
Cumulative error across 5 cycles tERR(5per) -250 250 -200 200 ps 35
Cumulative error across n cycles, n = 6....10,
inclusive tERR(6-10 per) -350 350 -300 300 ps 35
Cumulative error across n cycles, n = 11...50,
inclusive tERR(11-50 per) -450 450 -450 450 ps 35
Table 9 Specific Note 30
Parameter Symbol DDR2-1066 Units Notes
min max
Cumulative error across 2 cycles tERR(2per) -132 132 ps 30
Cumulative error across 3 cycles tERR(3per) -157 157 ps 30
Cumulative error across 4 cycles tERR(4per) -175 175 ps 30
Cumulative error across 5 cycles tERR(5per) -188 188 ps 30
Cumulative error across n cycles, n = 6....10, inclusive tERR(6-10 per) -250 250 ps 30
Cumulative error across n cycles, n = 11...50, inclusive tERR(11-50 per) -425 425 ps 30