Keysight Technologies D9020DDRC, Manual

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17 Command and Address Timing (CAT) Tests
318 DDR2(+LP) Compliance Testing Methods of Implementation
tVAC (CS, CA), Time Above V
IH(AC)
/Below V
IL(AC)
- Test Method of Implementation
The purpose of this test is to verify that the time the command/address signal is above V
IH(AC)
and
below V
IL(AC)
is within the conformance limits as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Require Read/Write separation: No
Signal(s) of Interest:
• Command/Address Signal (LPDDR2 only) OR
• Control Signal
Signals required to perform the test on the oscilloscope:
• Command/Address Signal OR
• Control Signal
Test Definition Notes from the Specification
Test References
See Table 107 - Required time tVAC above V
IH(AC)
{below V
IL(AC)
} for valid transition in the
JESD209-2B .
PASS Condition
The worst measured tVAC(CS, CA) should be within the specification limit.
Table 227 Required time tVAC above V
IH(AC)
{below V
IL(AC)
} for valid transition
Slew Rate tVAC @ 300 mV [ps] tVAC @ 220 mV [ps]
Min Max Min Max
>2.0 75 - 175 -
2.0 57 - 170 -
1.5 50 - 167 -
1.0 38 - 163 1
0.9 34 - 162 -
0.8 29 - 161 -
0.7 22 - 159 -
0.6 13 - 155 -
0.5 0 - 150 -
<0.5 0 - 150 -