Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
242 DDR2(+LP) Compliance Testing Methods of Implementation
tHZ(DQS) Test (Low Power), DQS Out HIGH Impedance Time From Clock - Test Method of Im -
plementation
The purpose of this test is to verify that the time when the DQS is no longer driving (from LOW state
to the high impedance stage), to the reference clock signal crossing, is within the conformance limits
as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQS signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The measured tHZ(DQS) shall be within the specification limit.
Table 165 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQS high-Z from
clock
*15
tHZ(DQS) Max
t
DQSCK
(max) - 100 ps