Keysight Technologies D9020DDRC, Manual

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14 Clock Timing (CT) Tests
206 DDR2(+LP) Compliance Testing Methods of Implementation
tDQSCKDM Test - DQSCK Delta Medium Test- Test Method of Implementation
The purpose of this test is to verify that the DQSCK difference within 1.6 μs must be within the
conformance limit as specified in the JEDEC specification. Each individual DQSCK is defined as time
interval from data strobe output (DQS Rising) first rising edge of sub-burst to the rising edge of the
clock that before tDQSCK delay (cycle) before nearest rising edge of the clock.
Signals of Interest
Signal cycle of interest: READ
Mode Supported: LPDDR2
Required Read/Write separation: Yes
Signal(s) of Interest:
• Data Strobe Signals (supported by Data Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS
Test Definition Notes from the Specification
Test References
See Table 103- LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The worst measured tDQSCKDM should be within the specification limit.
Table 125 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQSCK Delta
Medium
tDQSCKDM Max 680 780 900 1050 1350 1550 1800 1900 2000 2100 ps