Keysight Technologies D9020DDRC, Manual

Page: 214 / 370

14 Clock Timing (CT) Tests
198 DDR2(+LP) Compliance Testing Methods of Implementation
tDQSCK (Low Power), DQS Output Access Time from CK_t,CK_c - Test Method of Implemen -
tation
The purpose of this test is to verify that the time interval from the data strobe output’s (DQS rising
edge) first rising edge to the rising edge of the clock that is before the nearest rising edge of the
clock delayed tDQSCK Delay cycles, is within the conformance limit as specified in the JEDEC
specification.
Signals of Interest
Signal cycle of interest: READ
Mode Supported: LPDDR2, for DDR refer to tDQSCK Test.
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQS signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103- LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The measured tDQSCK should be within the specification limit.
Table 121 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQS output
access time
from CK_t/CK_c
tDQSCK
Min 2500 ps
Max 5500