DDR2(+LP) Compliance Testing Methods of Implementation
155
Differential Signals AC Input Parameters Tests
10
Measurement Algorithm
1 Acquire and split read and write bursts of the acquired signal. (See notes on DDR read/write
separation).
2 Take the first valid WRITE burst found.
3 Find all valid Strobe positive pulses in the burst. A valid Strobe positive pulse starts at 0 Volt
crossing at valid Strobe rising edge (see notes on threshold) and ends at the 0V crossing on the
following valid Strobe falling edge (see notes on threshold).
4 For the first valid Strobe positive pulse, zoom in on the pulse so that it appears on the
oscilloscope’s display, and perform the V
TOP
measurement. Take the V
TOP
measurement result as
the V
IHdiff(AC)
value.
5 Continue the previous step for the rest of the valid Strobe positive pulses that were found in the
burst.
6 Determine the worst result from the set of V
IHdiff(AC)
measured.
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...
