Keysight Technologies D9020DDRC, Manual

Page: 168 / 370

10 Differential Signals AC Input Parameters Tests
152 DDR2(+LP) Compliance Testing Methods of Implementation
V
IX(AC)
, AC Differential Input Cross Point Voltage Test for Clock -Test Method of Implementa -
tion
The purpose of this test is to verify the crossing point voltage value of the input differential test
signals pair is within the conformance limits of the V
IX(AC)
as specified in the JEDEC specification.
The value of V
DDQ
which directly affects the conformance lower limit is set to 1.8V for the compliance
limit set used. User may choose to use the UDL (User Defined Limit) feature in the application to
perform this test against a customized test limit set based on different values of V
DDQ
.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: No
Signal(s) of Interest:
• Clock Signals
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - Clock Signals
Test Definition Notes from the Specification
Table 97 Differential Input AC Logic Level
Symbol Parameter Min Max Units Notes
V
IX(AC)
AC differential cross point voltage 0.5 * V
DDQ
- 0.175 0.5 * V
DDQ
+ 0.175 V 2
Table 98 Differential Input AC Logic Level (DDR2-1066)
Symbol Parameter Min Max Units Notes
V
IX(AC)
AC differential cross point voltage 0.5 * V
DDQ
- 0.175 0.5 * V
DDQ
+ 0.175 V 2