Keysight Technologies D9020DDRC, Manual

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6 Single-Ended Signals VIH/VIL (Data, Mask) Tests
114 DDR2(+LP) Compliance Testing Methods of Implementation
V
ILDQ(AC)
- Test Method of Implementation
V
IL
Input Logic Low (Data, Mask) test can be divided into two subtests:
• V
ILDQ(AC)
test
• V
ILDQ(DC)
test
V
ILDQ(AC)
- AC Input Logic Low (Data, Mask).
The purpose of this test is to verify that the voltage level of the test signal at tDS (DM and DQ input
setup time in JEDEC specification) before the DQS midpoint is lower than the conformance lower
limits of the V
ILDQ(AC)
value specified in the JEDEC specification.
The value of V
REF
(which directly affects the conformance upper limit) is set to 0.6V for the
compliance limit set used. You may choose to use the User Defined Limit feature in the application to
perform this test against a customized test limit set based on different values of V
REF
.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Signals (supported by Data Strobe Signals) OR
• Data Mask Signals (supported by Data Strobe Signals)
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above.
• Supporting Pin - Data Strobe Signals
Test Definition Notes from the Specification
Test References
See Table 76 - Single-ended AC and DC Input Levels for DQ and DM in the JESD209-2B .
PASS Condition
The voltage level at tDS (DM and DQ input setup time in JEDEC specification) before the DQS
midpoint for the low level voltage shall be less than or equal to the maximum V
ILDQ(AC)
value.
Table 73 Single-ended AC and DC Input Levels for DQ and DM
Symbol Parameter LPDDR2-1066 to LPDDR2-466 LPDDR2-400 to LPDDR2-200 Units Notes
Min Max Min Max
V
ILDQ(AC)
AC input logic LOW Note 2 V
REF
- 0.220 Note 2 V
REF
- 0.300 V 1, 2, 5