DDR2(+LP) Compliance Testing Methods of Implementation
105
Single-Ended Signals VIH/VIL (Address, Control) Tests
5
V
ILCA(AC)
- Test Method of Implementation
V
IL
Input Logic Low (Address, Control) test can be divided into two subtests:
• V
ILCA(AC)
test
• V
ILCA(DC)
test
V
ILCA(AC)
- AC Input Logic Low (Address, Control).
The purpose of this test is to verify that the histogram mode low level voltage value of the test signal
within a valid sampling window is lower than the conformance lower limits of the V
ILCA(AC)
value
specified in the JEDEC specification.
The value of V
REF
(which directly affects the conformance upper limit) is set to 0.6V for the
compliance limit set used. You may choose to use the User Defined Limit feature in the application to
perform this test against a customized test limit set based on different values of V
REF
.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Command/Address Signals
• Chip Select Signals
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above.
Test Definition Notes from the Specification
Test References
See Table 74 - Single-ended AC and DC Input Levels for CA and CS_n Inputs in the
JESD209-2B
.
PASS Condition
The mode value for the low level voltage must be less than or equal to the minimum V
ILCA(AC)
value.
Measurement Algorithm
1 Obtain sample or acquire signal data.
2 Find all valid negative pulses. A valid negative pulse starts at V
REF
crossing at valid falling edge
and end at V
REF
crossing at the following valid rising edge (See notes on threshold).
3 Zoom in on the first valid negative pulse and perform V
BASE
measurement. Take the V
BASE
measurement results as V
ILCA(AC)
value.
4 Continue the previous step with another nine valid negative pulses.
5 Determine the worst result from the set of V
ILCA(AC)
measured.
Table 69
Single-ended AC and DC Input Levels for CA and CS_n Inputs
Symbol
Parameter
LPDDR2-1066 to LPDDR2-466
LPDDR2-400 to LPDDR2-200
Units
Notes
Min
Max
Min
Max
V
ILCA(AC)
AC input logic LOW
Note 2
V
REF
- 0.220
Note 2
V
REF
- 0.300
V
1, 2
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...