DV-5700/DVF-R9050/R9050-S
17
CIRCUIT DESCRIPTION
Port No.
Port Name
I/O
Function
Test outputs
112,113
TEST(00, 01)
O
These pins are test outputs and should be left unconnected in
normal operation.
Test inputs
41,50,51,108
TEST(0~5)
-
These pins are used for test purposes only and should always
109,111
be tied low for normal operation.
Power Supply Connections(Not shown on Block diagram)
1,33,63,73,84,
Pad Ring digital power connections. Connect to the d3.3
95,105,114,123,
VDD33
-
volt power supply and decouple to the digital ground plane.
137,144,151,167
2,17,34,55,64,
74,85,96,106,
VSS
-
Ground connections. Connect to the digital ground plane.
115,124,132,138,
145,152,159,168
43
AVSS
-
Ground connection for the clock PLL circuits.
Connect to the digital ground plane.
16,54,107,158
AVDD25
-
Core Logic digital power connections. Connect to the d2.5 volt power
supply and decouple to the digital ground plane.
Analog power connections for the clock PLL circuit.
42
AVDD
-
Connect to a separately dec2.5 volt power supply and decouple
directly to the AVSS pin.
Control Signals
49
RESETB
I
Reset. When this input is set low it will reset all the internal registers
to the default states.
When this pin is set high the outputs of the FL12200 will be enabled ; when
53
OE
O
it is set low the outputs will be set into a high-impedance state.
56~58
IFORMAT(2~0)
I
Input signal format control.
59~61
OFORMAT(2~0)
O
Output signal format control.
The settings of DADDR(1,0) allow the device address of the control
44,45
DADDR(1,0)
-
bus to be programmed to prevent conflict with the other devices
connected to the bus.
When this pin is set low the control bus will operate in the slave mode
-
; allowing the device to programmed from an external controller.
I
2-wire serial control bus data.
I/O
2-wire serial control bus clock.
I
Pixel clock input. This clock is used to drive all the circuits in the FL12200.
I/O
NTSC/PAL input or output.
I
No memory mode control input.
I
10-bit green or luminance signal input bus.
I
10-bit blue or Cb chroma signal input bus.
I
10-bit red or Cr chroma signal input bus.
35~39
R/CrIN(5~9)
3
HSYNCREFI
I
Horizontal sync or reference.
4
VSYNCREFI
I
Vertical sync or reference.
5
FIELDIN
I
Field identifier input.
Output Signals
65~72
G/YOUT(2~9)
O
Green or luminance output bus.
75,76
G/YOUT0,1
93,94
B/CbOUT8,9
O
Blue or Cb chrominance output bus.
97~104
B/CbOUT(0~7)
8. Video Deinterlacer : FL12200(X35, IC700)
8-1 Port Function
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