Keithley SourceMeter 2600B Series, Reference Manual

Page: 631 / 897

Section 7: TSP command reference Series 2600B System SourceMeter® Instrument Reference Manual
7-292 2600BS-901-01 Rev. C / August 2016
Also see
Status byte and service request (SRQ) (on page E-15)
status.condition (on page 7-275)
status.system.* (on page 7-347)
status.operation.*
These attributes manage the operation status register set of the status model.
Type TSP-Link accessible Affected by Where saved Default value
Attribute - - - - - - - -
.condition (R) Yes Not applicable Not saved Not applicable
.enable (RW) Yes Status reset Not saved 0
.event (R) Yes Status reset Not saved 0
.ntr (RW) Yes Status reset Not saved 0
.ptr (RW) Yes Status reset Not saved 31,769 (All bits set)
Usage
operationRegister
= status.operation.condition
operationRegister = status.operation.enable
operationRegister = status.operation.event
operationRegister = status.operation.ntr
operationRegister
= status.operation.ptr
status.operation.enable = o
perationRegister
status.operation.ntr = o perationRegister
status.operation.ptr = o perationRegister
operationRegister The status of the operation status register; a zero (0) indicates no bits set (also send
0 to clear all bits); other values indicate various bit settings
Details
These attributes read or write the operation status registers.
Reading a status register returns a value. The binary equivalent of the returned value indicates which
register bits are set. The least significant bit of the binary number is bit B0, and the most significant bit
is bit B15. For example, if a value of 2.04 (which is 20,480) is read as the value of the
condition register, the binary equivalent is 0101 0000 0000 0000. This value indicates that bit B14
( PROGRAM_RUNNING ) and bit B12 (USER) are set.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
** > > > > > > > > > > > > > > *
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0
* Least significant bit
** Most significant bit
For information about .condition, .enable, .event, .ntr, and .ptr registers, refer to
Status register set
contents (on page E-1) and Enable and transition registers (on page E-19). The individual bits of this
register are defined in the following table.