Keithley KPCMCIA-12AIAOH, User Manual

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3-4 Theory of Operation KPCMCIA-12AIAOH User’s Manual
Trigger circuit
The KPCMCIA-12AIAOH PC card can be triggered by the software (i.e., an internal trigger), an
external TTL input,* the analog input passing through the preset threshold, or the pacer clock.
For the TTL or analog trigger, an active trigger edge can be selected for either the low-to-high
transition or the high-to-low transition.
In one-shot trigger mode, one trigger, either internal or external, starts one scan of all the channels
specified in the scan list. The pacer clock does not have any effect in this mode. Multiple scans
can be set up by issuing (or receiving) multiple triggers.
In continuous trigger mode (without pre-trigger), a software, TTL, or analog trigger starts a series
of scans in which the first is initiated immediately upon receiving the trigger and the rest occur
each time the pacer clock fires. The process continues until the software issues an A/D stop
command.
If the internal trigger (or the software trigger) is selected, a trig/arm command from software
serves as a trigger as soon as it is received by the PC card. For the external trigger sources (TTL
or analog), the same command is taken as an arm command, which arms the PC card so the first
proper trigger edge since the reception of the arm command serves as the trigger. Any trigger
edges before the first one will be ignored. Unexpected edge transitions during the configuration
of the trigger source and edge will not be taken as triggers as long as the PC card is not armed.The
pre-trigger option can be selected in continuous mode (not allowed in one-shot mode) with exter-
nal trigger sources (TTL or analog but not with internal trigger). If the option is selected, the arm
command will actually start the pacer clock so the input channels specified in the scan list are
scanned each time the pacer clock fires and the scan results are placed in the data FIFO. However,
once the almost-full threshold (programmed as an integer multiple of the scan list length) of the
data FIFO is reached, the least recent scan is automatically discarded and the most recent one is
placed in the data FIFO. This filling and discarding continues until the external trigger (TTL or
analog) activates. At that point, no more discarding will be performed, and the normal data acqui-
sition process starts with half FIFO full of data samples right before the trigger. A/D event bits
are not set until the trigger activates, guaranteeing that no interrupts can be sent before the trigger
eventually activates.
*NOTE In “Paced” mode, the same input pin is shared between external clock
and external trigger, hence only one function can be used (not both si-
multaneously).
A/D converter and data FIFO
The KPCMCIA-12AIAOH PC card always assumes a bipolar input range of ±10V if the gain is
one. The output data format will always be in 2’s complement (and left justified for 12-bit ver-
sions). The data acquisition time of the A/D converter is 2µs, while its conversion time is no more
than 8µs. The A/D converter output is fed into the data FIFO providing data buffering of 2048
samples.
The hardware design guarantees that the A/D converter, once triggered, will perform a conversion
for every analog input channel specified in the scan list at the selected scan speed and feed the
results into the data FIFO. In between scans, the PC card waits until another trigger activates (one-
shot mode) or the pacer clock fires (continuous mode).
The data FIFO has two programmable thresholds: one for almost full and the other for almost
empty. The KPCMCIA-12AIAOH PC card only uses the almost-full threshold and ignores the
other. Upon power up or reset, the almost-full threshold is defaulted to 7 bytes to full (3.5 samples).
When the FIFO is full, no more samples can be written into the FIFO. At the end of each scan,
the KPCMCIA-12AIAOH PC card sets a data-lost flag if the data FIFO is already full.