Keithley KPCI-PIO24, User Manual, Page: 32 / 66

4-4 Interrupts and I/O Address Mapping KPCI-PIO24 User’s Manual
Table 4-2
Control register bit assignments for each port group
Three different data transfer modes can be specified via appropriate combinations of bits 6 and 7.
Refer to Table 4-3.
NOTE Some of the terms that follow may not be fully understood without
referring to the AMCC S5933 PCI Bus Controller manual.
Configuration for this port
Bit When bit When bit
Number Function Variable name for bit value = 0
1
value = 1
Bit 7 Transfer method bit 1 ACCESSMODE1 See Table 4-3 See Table 4-3
Bit 6 Transfer method bit 0 ACCESSMODE2 See Table 4-3 See Table 4-3
Bit 5 External interrupt
polarity INT_POLARITY See footnote
2
See footnote
3
Bit 4 Nonlatching/latching
ports BUFF_LATCH See footnote
4
See footnote
5
Bit 3 I/O direction for PC
port, upper half PCHI0_DIR Input Output
Bit 2 I/O direction for PC
port, lower half PCLO0_DIR Input Output
Bit 1 I/O direction for PB port PB0_DIR Input Output
Bit 0 I/O direction for PA port PA0_DIR Input Output
1
All bit values default to ‘0’ upon computer reset or power-up.
2
When INT_POLARITY = 0, an interrupt is triggered by the positive (rising) edge of the
external interrupt signal at pin 1 of the I/O connector.This is the default upon reset or power-up.
3
When INT_POLARITY = 1, an interrupt is triggered by the negative (falling) edge of the
interrupt signal.
4
When BUFF_LATCH = 0, ports configured for input act as transparent buffers; data is read
from the ports in real time. This is the default upon reset or power-up.
5
When BUFF_LATCH = 1, ports configured for input act as latches; data is latched when an
external interrupt signal is received, at pin 1 of the I/O connector. The polarity is defined
by INT_POLARITY.