Keithley 707B, Reference Manual

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Models 707B and 708B Switching Matrix Reference Manual Appendix C: Status model
707B-901-01 Rev. A / August 2010 C-9
As an example, when a print command is sent, the response message is placed in the Output queue.
When data is placed in the Output queue, the Message Available (MAV) bit in the Status Byte
Register sets. A response message is cleared from the Output queue when it is read. The Output
queue is considered cleared when it is empty. An empty Output queue clears the MAV bit in the
Status Byte Register.
A message is read from the Output queue by addressing the Switching Matrix to talk.
Event summary bit (ESB register)
The summary bit of the Standard event register provides enabled summary information to Bit 5 (OSB)
of the status byte.
Event summary bit (Standard event register)
Figure 101: Event summary bit (Standard event register)
See the Event Summary Bit
in the Status Byte register overview.
0
6
5
3
4
2
1
7
Event Summary Bit
*
status.standard.event
status.standard.enable
&
Legend
Summary Message Bit: A single bit indicating one or more enabled
events occured.
Performs a logical AND of input bits, with the result feeding the
Summary Message Bit.
Bit not used (returns a value of 0 when read).
+
&
status.standard.OPC
status.standard.QYE
status.standard.DDE
status.standard.EXE
status.standard.CME
status.standard.URQ
status.standard.PON
+
As shown above, there is only one register set associated with the event status register. Attributes are
summarized in
status.standard.* (on page 7-188). Keep in mind that bits can also be set by using
numeric parameter values. For details, see Programming enable and transition registers (on page C-
13).
For example, any of the following statements will set the operation complete enable bit:
standardRegister = status.standard.OPC
status.questionable.enable = status.standard.OPERATION_COMPLETE
status.questionable.enable = 1