Keithley 6512, Instruction Manual

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Theory of Operation
6-9
is developed by connecting one end of R149H to +5V
through U136B. As long as the integrator output remains
positive, the Q2 pulses from U127 are transmitted to the mi-
croprocessor, where they are counted to be used in the final
reading. Once the single-slope comparator output goes low,
the Q2 pulses are turned off by U135C.
6.6 Digital circuitry
Model 6512 operation is controlled by the internal micro-
computer and associated firmware. The following para-
graphs briefly describe the various aspects of the digital
circuitry. Descriptions are keyed to the digital circuitry sche-
matic (drawing number 6512-106, page 2) located at the end
of Section 8.
6.6.1 Microcomputer
Microcomputer operation centers around the 8 bit 146805
CMOS microprocessor, U1
0
9. This device utilizes an 8-bit
data bus and incorporates a multiplexed data/address bus for
the lower eight bits of the 12-bit address bus. The 146805 has
112 bytes of on-chip memory, two 8-bit I/O ports, and is ca-
pable of directly addressing 8K bytes of memory. The MPU
has direct control over the display, front panel switches, an-
alog-to-digital converter, the IEEE-488 bus, as well as the
Meter Complete output and the External Trigger Input.
Microprocessor timing is performed by Y101, a 3.2768MHz
crystal. The signal is internally divided by five to obtain a bus
operating frequency of 655.36kHz. This signal is present at
the AS terminal of the processor and is used as a control sig-
nal to strobe the lower ordered eight bits of the address into
the address latch, U108. A 655.36kHz signal is also present
at the DS terminal to act as a system clock.
6.6.2 Memory elements
Firmware for the Model 6512 is stored in U106, a 27128 16K
×
8 PROM. Temporary storage is afforded by U107, a 6116
2K
×
8 RAM IC. The MPU uses the RAM for temporary
storage, as well as for data store readings. Calibration con-
stants, the display mode, and the IEEE-488 primary address
are stored in the NVRAM, U104. During the power-up cycle,
NVRAM data is transferred to normal RAM to allow easier
access during operation. While data transmission to the
ROM and RAM are done in parallel, NVRAM data transmis-
sion is performed serially.
6.6.3 Device selection
The 146805 processor can directly address only 8K bytes of
memory. The Model 6512 requires greater addressing capa-
bility, as 16K of ROM, 2K of RAM, and other memory space
requirements are present in the system. To get around this
limitation, device selection circuitry is incorporated with the
microcomputer.
Device selection is performed by elements of U111, U112,
U117, and U118. MPU lines used as part of the selection pro-
cess include the A10-A12 address lines, the PB6 line, the PB7
line, and the DS line. Signals generated by this circuitry in-
clude a line that controls the ROM chip select, a signal line that
controls the RAM chip select, and circuitry which enables the
display control and IEEE-488 bus circuits. Additional device
selection signals include the memory paging signals. Two sig-
nals divide the 16K ROM area into 4K pages, while the a third
signal divides the 2K RAM area into two 1K pages.
Because of the paging scheme employed, several devices can
occupy a given address within the microprocessor’s address-
ing space. Table 6-1 gives the general address range for each
device.
6.6.4 IEEE-488 bus
The Model 6512 has a standard IEEE-488 interface that al-
lows the instrument to be programmed from a system con-
troller. Commands can be sent over the bus to the instrument,
and data can be requested from the instrument as well.
The IEEE-488 interface is made up of U113, U119, and
U120. U113 is a 9914 GPIA (General Purpose Interface
Table 6-1
Memory mapping
Device Address range
RAM (U107)
ROM (U106)
Display Control (U110)
Display Control (U116)
IEEE-488 Bus (U113) 000
H
-03FF
H
0800
H
-1FFF
H
0412
H
040A
H
0418
H
-041F
H