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38

Operation & Calibration

3.1.8

Isolation

The USB-61210 provides 500VDC isolation capability to protect against

hazardous voltage caused by erroneous signal connection or signal lev

-

els to be measured exceeding expectation. The isolation circuit can also

reduce the ground-loop noise.

Figure 3-25: Isolation

3.2 Calibration

3.2.1

Loading Calibration Constants

The  USB-61210  is  factory-calibrated  before  shipment.  The  associated

calibration  constants  of  the  TrimDACs  firmware  are  written  to  the

onboard  EEPROM.  TrimDACs  firmware  is  the  algorithm  in  the  FPGA.

cnt

length

Pulse

cnt

initial

Pulse

cnt

length

Pulse

Duty

cnt

length

Pulse

cnt

initial

Pulse

F

F

PWM

Tim ebase

PWM

_

_

_

_

_

_

_

_

_

_

+

=

+

=

Summary of Contents for USB-61210

Page 1: ...Advance Technologies Automate the World Manual Rev 1 00 Revision Date July 31 2017 USB 61210 4 CH 16 Bit 2MS s Simultaneous Sampling USB DAQ Module User s Manual...

Page 2: ...ii...

Page 3: ...mentation even if advised of the possibility of such damages Environmental Responsibility JYTEK is committed to fulfill its social responsibility to global environ mental preservation through complian...

Page 4: ...NOTE NOTE Additional information aids and tips that help users perform tasks CAUTION Information to prevent minor physical injury component damage data loss and or program corruption when trying to co...

Page 5: ...2 Analog Input 3 1 5 Schematics 4 1 5 1 Module 4 1 5 2 Module Stand 7 1 6 Connector Pin Assignment 11 1 6 1 Connector Signal Description 11 1 7 Analog Input Signal Connection 12 1 8 Software Support...

Page 6: ...Conversion 22 3 1 3 Trigger Sources 25 3 1 4 Trigger Modes 27 3 1 5 Programmable Function I O 31 3 1 6 Basic Timer Counter Function 32 3 1 7 General Purpose Timer Counter Modes 33 3 1 8 Isolation 39 3...

Page 7: ...18 Figure 2 6 USB 61210 module in Windows Device Manager 19 Figure 2 7 Device ID Selection Control 20 Figure 3 1 Carrier Board Functional Block Diagram 21 Figure 3 2 Daughter Board Functional Block Di...

Page 8: ...red Continuous Pulse 37 Figure 3 21 Mode 8 Continuous Gated Pulse 37 Figure 3 22 Mode 9 Edge Separation Measurement 38 Figure 3 23 Mode 10 PWM Output Following Trigger 38 Figure 3 24 Mode 10 PWM Outpu...

Page 9: ...ble 1 1 USB 61210 Pin Assignment 11 Table 1 2 CN1 CN2 I O Signal Description 12 Table 3 1 Bipolar Analog Input Range and Output Digital Code 23 Table 3 2 Pin Definition of LVTTL Digital I O 31 Table 3...

Page 10: ...x List of Tables This page intentionally left blank...

Page 11: ...th removable screw down terminals for easy device connectivity and the included multi functional stand can be used for desktop rail or wall mounting Suitable for high speed data acquisition laboratory...

Page 12: ...on I O 8 CH LVTTL DI and 4 CH LVTTL DO 2 CH 32 bit general purpose timer counters Clock source internal or external Max source frequency internal 80 MHz exter nal 10 MHz 2 CH PWM outputs Duty cycle 1...

Page 13: ...ain 5 SINAD fin 10 kHz 89 dB gain 1 5 THD fin 10 kHz 100 dB gain 1 5 SNR fin 10 kHz 89 dB gain 1 5 ENOB fin 10 kHz 14 3 Bit gain 1 5 Temperature Drift Gain Error 5 ppm C gain 1 5 Temperature Drift Off...

Page 14: ...4 Introduction 1 5 Schematics 1 5 1 Module Figure 1 1 USB 61210 Module Rear View Data transfer Programmed I O continuous USB bulk transfer mode NOTE NOTE All units are in millimeters mm...

Page 15: ...Introduction 5 Figure 1 2 USB 61210 Module Side View...

Page 16: ...6 Introduction Figure 1 3 USB 61210 Module Front View...

Page 17: ...desk rail or wall mounting To fix the module in the stand slide the module body into the stand until a click is heard To remove the module from the stand twist the bottom of the stand in a back and fo...

Page 18: ...8 Introduction Figure 1 5 Module Stand Wall Mount Kit Side View w connections Figure 1 6 Module in Stand Front View...

Page 19: ...Introduction 9 Figure 1 7 Module Stand Top View 20 4 20 4 B 26...

Page 20: ...10 Introduction Figure 1 8 Module Stand Side Cutaway View Figure 1 9 Module Stand Front View 5 89 1 5 6 3 4 100...

Page 21: ...IGND 20 40 IGND GPI0 19 39 GPO0 GPI1 18 38 GPO1 GPI2 17 37 GPO2 GPI3 16 36 GPO3 GPI4 15 35 IGND GPI5 14 34 CONV GPI6 13 33 IGND GPI7 12 32 AITG IGND 11 31 NC IGND 10 30 IGND AI0 9 29 AI2 AI0 8 28 AI2...

Page 22: ...way to the existing ground system A device with an isolated output is a floating signal source This includes optical isolator outputs transformer outputs and thermocouples Ground Referenced A ground...

Page 23: ...ended mode Figure 1 10 GRND Referenced Source w DIFF Input Connection of a floating signal source to the USB 61210 module in differential input mode is further shown For floating signal sources the n...

Page 24: ...K for customized DAQ application development USB DASK enables you to perform detailed operations and achieve superior performance and reli ability from your data acquisition system DASK kernel drivers...

Page 25: ...returning any product to JYTEK Ensure that the following items are included in the package USB 61210 module Stand Two removable screw terminals USB cable 2 meter length Rail mount kit 2 2 Attaching th...

Page 26: ...16 Getting Started 2 3 Rail Mounting The multi function stand can be mounted on the DIN rail using the rail mount kit as shown Figure 2 1 Rail Mount Kit Figure 2 2 Module Pre Rail Mounting...

Page 27: ...3 Module Rail Mounted 2 4 Wall Mounting The multi function stand can be fixed to a wall using four flush head screws as shown The four screw holes should be approximately 3 4 mm in diameter Figure 2 4...

Page 28: ...ware message appears It will take around 6 seconds to load the firmware When loading is complete the LED indica tor on the rear of the USB DAQ module changes from amber to green and the New Hardware m...

Page 29: ...e USB port may be insufficient The USB 61210 module is exclusively powered by the USB port and requires 460 mA 5 V 2 5 2 Device ID A rotary control on the rear of the module as shown controls device I...

Page 30: ...D to avoid conflicts and errors in operation Figure 2 7 Device ID Selection Control 2 5 3 Hardware Configuration All remaining hardware configurations are software programmable including sampling upda...

Page 31: ...ow temperature drift signal acquisition Calibration data is saved in the EEPROM Figure 3 1 Carrier Board Functional Block Diagram FPGA ADC Control Trigger Control Data Processing 8051 Core Function PC...

Page 32: ...predefined trigger source Data acquisition will commence once a trigger condition is matched After A D conversion A D data is buffered in a data FIFO for transfer into system memory for further proces...

Page 33: ...a single A D data sample the A D converter starts a conversion when the dedicated software Description Bipolar Analog Input Range Digital Code Full scale range 10 V 2 V N A Least significant bit 305...

Page 34: ...ion clock pin While the conversion clock source can be chosen by setting AI source configuration if precision acquisition is required use of the internal hardware timer is recommended Sampling Rate Co...

Page 35: ...3 Trigger Sources Software Triggering This trigger mode requires no external trigger source The trigger asserts immediately following execution of the specified function calls to begin the operation E...

Page 36: ...3 5 Below Low Analog Triggering Above High Analog Triggering In above high analog triggering as shown the trigger signal is gener ated when the input analog signal exceeds the High_Threshold volt age...

Page 37: ...etrigger and delay trigger with retrigger modes Post Trigger Acquisition Mode no retriggering Post trigger acquisition is indicated when data is to be collected after the trigger event as shown Figure...

Page 38: ...ividually M and N samples as shown Figure 3 10 Middle Trigger Pre Trigger Mode Pre trigger acquisition is indicated when data is to be collected before the trigger event Acquisition commences once spe...

Page 39: ...nal occurs another N samples are performed The process repeats until the specified number of re trigger signals are detected Figure 3 12 Post Trigger with Retriggering Gated Trigger Gated trigger acqu...

Page 40: ...l programmable I O function provided by an FPGA chip configurable as LVTTL DI DO 32 bit timer counters and PWM output These signals are single ended and 5 V LVTTL compli ant LVTTL DI DO Programmable f...

Page 41: ...ammable gate selection hardware or software control Programmable input and output signal polarities high active or low active Initial Count loaded from a software application Current count value reada...

Page 42: ...vity all GPTC_CLK GPTC_GATE and GPTC_OUT in the fol lowing illustrations are assumed to be active high or rising edge triggered 3 1 7 General Purpose Timer Counter Modes Ten programmable timer counter...

Page 43: ...ges of GPTC_GATE After the completion of the period interval on GPTC_GATE GPTC_OUT outputs high and then current count value can be read by the software applica tion Operation in which initial count 0...

Page 44: ...4 Single Gated Pulse Generation This mode generates a single pulse with programmable delay and pro grammable pulse width following software start The two programma ble parameters can be specified in t...

Page 45: ...Mode 5 Single Triggered Pulse Mode 6 Re Triggered Single Pulse Generation This mode is similar to Mode 5 except that the counter generates a pulse following every active edge of GPTC_GATE After softwa...

Page 46: ...E enables disables calculation When GPTC_GATE is inactive the counter halts the current count value Generation of two pulses with a pulse delay of four and a pulse width of three is shown Figure 3 21...

Page 47: ...tting a varying amount of Pulse_initial_cnt and Pulse_length_cnt varying pulse frequencies Fpwm and duty cycles Dutypwm can be obtained PWM output is shown Figure 3 23 Mode 10 PWM Output Following Tri...

Page 48: ...t can also reduce the ground loop noise Figure 3 25 Isolation 3 2 Calibration 3 2 1 Loading Calibration Constants The USB 61210 is factory calibrated before shipment The associated calibration constan...

Page 49: ...ility measures and corrects almost all cali bration errors with no external signal connections reference voltage or measurement devices The USB 61210 provides onboard calibration ref erence to ensure...

Page 50: ...40 Operation Calibration...

Page 51: ...rn off power and unplug any power cords cables To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity...

Page 52: ...serviced by authorized technicians when The power cord or plug is damaged Liquid has penetrated the equipment It has been exposed to high humidity moisture It is not functioning or does not function a...

Page 53: ...hard drives flash cards etc please back up your data before send ing them for repair JYTEK is not responsible for any loss of data Please ensure the use of properly licensed software with our systems...

Page 54: ...age environments i e high temperatures high humidity or volatile chemi cals Damage caused by leakage of battery fluid during or after change of batteries by customer user Damage from improper repair b...

Page 55: ...tact us should you require any service or assistance SHANGHAI JYTEK CO LTD Web Site http www jytek com Sales Service service jytek com Telephone No 86 21 50475899 Fax No 86 21 50475899 Mailing Address...

Page 56: ...46 Getting Service...

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