JYTEK Thunderbolt PXIe-62314T, Manual

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4 Introduction
PXIe 100 MHz System Reference Clock (PXIe_CLK100)
Table 1-4: PXI Express 100 MHz System Reference Clock
Item Description
Maximum slot-to-slot skew 100 ps
Accuracy ±1 ppm max, 0°C to 55°C (32°F to 131°F)
Maximum jitter 2.41 ps RMS phase-jitter (12kHz–20MHz)
Duty-factor for PXIe_CLK100 45% to 55%
Absolute differential voltage
(when terminated with a 50Ω load to
1.30 V or Thévenin equivalent)
400 to 900 mV
PXIe_SYNC100 Implemented as default behavior.
PXIe_SYNC_CTRL is disabled by
connecting a 10kΩ pull-down resistor to
ground.