JYTEK PXIe-2722, User Manual

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PXIe-2722 Chassis | jytek.com | 6
Figure 5 Trigger Bus Buffer Routing
Note:

The triangle shown represents the direction of the trigger.

The trigger bus buffer routing can be configured via the JYDM utility.
2.1.6 PXI Local Bus
The local bus on PXIe-2722 is a daisy-chained bus that connects each peripheral slot
with adjacent peripheral slots to the left and right, which by routing PXI Local Bus 6
signal between adjacent peripheral slots.
2.1.7 System Reference Clock and Synchronization Signal
The PXIe-2722 backplane supplies 10MHz reference clock (PXI_CLK10), 100MHz
reference clock (PXIe_CLK100) and synchronization signal (PXIe_SYNC100) to each
peripheral slot for inter-module synchronization.
The PXI_CLK10 and PXIe_CLK100 clocks are in-phase according to the PXI-5
specification. A phase-lock loop (PLL) circuit on the backplane synchronizes the
PXI_CLK10 and PXIe_CLK100 clock.
There are two 10 MHz reference clock source:

Built-in 10 MHz clock source on backplane.

External 10 MHz clock through front panel’s SMA connector.
The PXIe-2722 automatically selects the 10 MHz reference clock source and its
priority as follows.
SMA Connector on Front Panel 10MHz Clock Source of Peripheral Slots
No clock present Backplane’s local oscillator
10MHz clock present SMA connector
Table 2 Reference Clock Priority
The PXIe-2722 has the default timing relationship of PXI_CLK10, PXIe_CLK100 and
PXIe_SYNC100 as show in Figure 4 which comply with PXI-5 specification.