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JYTEK PCIe/PXIe-6302, User Manual

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JYTEK PCIe/PXIe-6302 User Manual Download Page 48

PCIe/PXIe-6302 |

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hardware driver architecture, FirmDrive, upon which many our future hardware will
be based.

In addition to our own developed hardware, JYTEK also rebrands Adlink’s PXI product
lines. In addition, JYTEK has other rebranding agreements to increase our hardware
coverage. It is our goal to provide the complete product coverage in PXI and PCI
modular instrumentation and data acquisition.

8.4

JYTEK Software Platform

JYTEK has developed a complete software platform, SeeSharp Platform, for the test
and measurement applications. We leverage the open sources communities to
provide the software tools. Our platform software is also open sourced and is free,
thus lowering the cost of tests for our customers. We are the only domestic vendor
to offer complete commercial software and hardware tools.

8.5

JYTEK Warranty and SupportServices

With our complete software and hardware products, JYTEK is able to provide
technical and sales services to wide range of applications and customers

.

In most

cases, our products are backed by a 1-year warranty. For technical consultation,
pre-sale and after-sales support, please contact JYTEK of your country.

Summary of Contents for PCIe/PXIe-6302

Page 1: ...PCIe PXIe 6302 24 bits High Resolution Thermocouple Input Module User Manual User Manual Version V1 9 3 Revision Date Jan 17 2022...

Page 2: ...curacy 11 3 2 Temperature Accuracy 16 4 Software 17 4 1 System Requirements 17 4 2 System Software 17 4 3 C Programming Language 18 4 4 6302 Hardware Driver 18 4 5 Install the SeeSharpTools from JYTEK...

Page 3: ...YPEDIA Information 2 Figure 2 TB 68CJ terminal block 3 Figure 3 TB 68CJ Pin Define 4 Figure 4 6302 System Block Diagram 5 Figure 5 Themocouple connection 6 Figure 6 PXIe PCIe 6302 Front Panel 9 Figure...

Page 4: ...Reference Trigger Mode 38 Figure 35 Retrigger Complete State 38 Figure 36 SSI Connector in PCIe 6302 39 Figure 37 DIP Switch in PCIe 6302 40 Table 1 63xx on different buses 5 Table 2 6302 channel gro...

Page 5: ...chanism optimized for voltage measurement the PCIe PXIe 6302 has an optimum voltage measurement offset error of up to 1 V and a voltage measurement gain error of 2 ppm PCIe PXIe 6302 has a very low te...

Page 6: ...t select JY6302_Examples zip This will lead you to download the sample program for this device In addition to the download information JYPEDIA also has a lot of other valuable information JYTEK highly...

Page 7: ...is plugged in a desktop computer The PCIe PXIe 6302 is connected to a TB 68CJ terminal block Figure 2 TB 68CJ terminal block The TB 68CJ has 4 terminal columns J1 J4 are shown below as Figure 3 In th...

Page 8: ...PCIe PXIe 6302 jytek com 4 Figure 3 TB 68CJ Pin Define...

Page 9: ...tem Block Diagram Figure 4 shows the system diagram of the 6302 The system is mainly composed of ADC DDR and FPGA control modules The FPGA based driver code provides a stable and efficient PCIe PXIe U...

Page 10: ...J has build in temperature sensors for measuring cold juntion temperature to achieve cold junction compensation CJC The terms hot junction and cold junction are used in this manual which also called m...

Page 11: ...PCIe PXIe 6302 jytek com 7 2 3 Specification 2 3 1 Input Characteristics...

Page 12: ...PCIe PXIe 6302 jytek com 8 Table 3 Input Characteristics 2 3 2 Timing and Trigger Table 4 Timing and Trigger Specification 2 3 3 Physical and Environment...

Page 13: ...e 5 Physical and Environment 2 4 Front Panel conections and Pinout Definition Figure 6 PXIe PCIe 6302 Front Panel PCIe PXIe 6302 provides 32 channels of thermocouple measurements and 4 digital input c...

Page 14: ...PCIe PXIe 6302 jytek com 10 Table 6 Pinout defination...

Page 15: ...PCIe PXIe 6302 jytek com 11 3 Performance Test 3 1 Voltage Accuracy Table 7 Voltage Accuracy Figure 7 Typical Error 30mV Input Figure 8 Typical Error 65mV Input...

Page 16: ...PCIe PXIe 6302 jytek com 12 Table 8 Input noise Figure 9 Typical Noise Level 0 Figure 10 Typical Noise Level 1...

Page 17: ...PCIe PXIe 6302 jytek com 13 Figure 11 Typical Noise Level 2 Figure 12 Typical Noise Level 3...

Page 18: ...PCIe PXIe 6302 jytek com 14 Figure 13 Typical Noise Level 4 Figure 14 Typical Noise Level 5...

Page 19: ...PCIe PXIe 6302 jytek com 15 Table 9 Input Stability Figure 15 Typical Drift 30mV Input Figure 16 Typical Drift 60mV Input...

Page 20: ...PCIe PXIe 6302 jytek com 16 3 2 Temperature Accuracy Temperature Accuracy Table 10 Temperature Accuracy Measurement sensitivity Table 11 Measurement sensitivity...

Page 21: ...he best support the following Linux versions Table 12 Supported Linux Versions 4 2 System Software When using the PCIe PXIe 6302 in the Window enviornment you need to install the following software fr...

Page 22: ...dware has a C hardware specific driver This driver provides rich and easy to use C interfaces for users to operate various 6302 function JYTEK has standardized the ways JYTEK and other vendor s DAQ ca...

Page 23: ...n your C programs in a Linux environment If you want to use your own Linux development system other than Mono you can do it using our Linux driver However JYTEK does not have the capability to support...

Page 24: ...e provide source code of our examples In many cases you can modify the source code and start to write your applications 5 2 AI Operations When performing AI operations it will be helpful if you unders...

Page 25: ...hannels Figure 17 shows a typical channel scan sequence In this case the user adds all channels Ch0 Ch31 in sequence and these channels are automatically assigned to four ADCs At the beginning of the...

Page 26: ...he order of added channels 5 2 2 ADC Timing Modes The ADC inside 6302 has a built in digital filter and multiple filter options Filter options affect the data output rate and 50 Hz 60 Hz rejection and...

Page 27: ...cally limit the highest sampling rate according to the number of added channels and the specific rate level If the user setsampling rate exceeds the limit the driver will automatically revise it For a...

Page 28: ...PCIe PXIe 6302 jytek com 24 Figure 19 AI Continuous Raw Data Paraments Click Start The result is shown below...

Page 29: ...Raw Data Acquisition Now change the mode of Timing Mode to Level5 and click Start A message will appear in the lower left corner as shown Figure 21 Acquisition State Choosing different modes in Timing...

Page 30: ...ampling rate of PCIe PXIe 6302 is 0 275 Samples s and the highest sampling rate is 800 Samples s The actual maximum sampling rate is according to the rate level and the number of channels added by eac...

Page 31: ...ate according to the following formula max number of channels on any one ADC Among them Current actual total sampling rate max number of channels on any one ADC Maximum number of channels added on a s...

Page 32: ...an check whether the TB 68CJ is properly connected When the acquisition task is started the driver will automatically confirm whether the TB 68CJ on the two connectors are connected reliably If the TB...

Page 33: ...the connection status of the thermocouple When the user calls the method PerformOpenThermocoupleDetection the PCIe PXIe 6302 outputs 0 5 A 2 A 4 A software configurable excitation current on all TC t...

Page 34: ...PCIe PXIe 6302 jytek com 30 Figure 24 Open Thermocouple Detection Status indicates the current working state of the channel...

Page 35: ...ust be longer then 20 ns for effective trigger The module will monitor the signal on digital trigger source and wait for the rising edge or falling edge of digital signal which depends on the set trig...

Page 36: ...PCIe PXIe 6302 jytek com 32 Figure 26 Digital Trigger Paraments Trigger Source must match the pin on the terminal block There are two Trigger Conditions Rising and Falling The result shows below...

Page 37: ...om 33 Figure 27 Digital Trigger Acquisition Since the squarewave is used for the digital trigger source when a rising edge of the squarewave occurs the digital trigger will be activated and the data a...

Page 38: ...k will start to acquire the signal immediately after the trigger asserted as shown in Figure 28 The Start Trigger mode is suitable for continuous acquisition and finite acquisition mode Figure 28 Star...

Page 39: ...e 6302 jytek com 35 Figure 29 AI Continuous Paraments When Start is clicked it generates a start trigger which starts the acquisition The result is shown below Figure 30 Signel Channel Continuous Acqu...

Page 40: ...igger mode is only suitable for finite acquisition mode The default number of pretrigger samples is 0 SampleToAcquire 1000 PreTriggerSamples 10 Posttrigger samples 1000 10 990 Figure 31 Reference Trig...

Page 41: ...2 and 5 6 3 Connect the K type Thermocouple s positive pole and negative pole to Terminal Block s TCO Pin 35 and TCO Pin 1 then connect the signal source s positive pole and negative pole to PCIe PXIe...

Page 42: ...Trigger Samples are 10 Click Start to begin the data acquisition the result is shown below Figure 34 Retrigger In Reference Trigger Mode Because the measured waveform is an irregular continuous line t...

Page 43: ...tional bus and it can synchronize up to four PCIe modules One PCIe module is designated as the master module and the other PCIe modules are designated as the slave modules Figure 36 SSI Connector in P...

Page 44: ...want to set the card number to 3 you could turn the position 2 and 1 of the DIP switch to the ON position and the orthers to OFF Find the detail below Figure 37 DIP Switch in PCIe 6302 Table 16 Relati...

Page 45: ...YTEK 6302 boards are precalibrated before the shipment We recommend you recalibrate 6302 board periodically to ensure the measurement accuracy A commonly accepted practice is one year If you need to r...

Page 46: ...ion 3 5 There is no guarantee that JYTEK python drivers will work correctly with other versions of Python If you want to be our paNEGer to support different Python platforms please contact us 7 2 C JY...

Page 47: ...TEK products Together with Adlink Technologies and JYTEK China JYTEK is expanding to other countries Each JYTEK location is an independently owned and operated franchise It shares JYTEK s philosophy a...

Page 48: ...latform SeeSharp Platform for the test and measurement applications We leverage the open sources communities to provide the software tools Our platform software is also open sourced and is free thus l...

Page 49: ...or non infringement of intellectual property rights unless such disclaimer is legally invalid JYTEK is not responsible for any incidental or consequential damages related to performance or use of this...

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