JYTEK PCIe-69834, User Manual

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Operations 23
3.6 ADC Timing Control
3.6.1 Timebase Architecture
Figure 3-11: Timebase Architecture
3.6.2 Basic Acquisition Timing
The PCIe-
69834
commences acquisition upon receipt of a
trigger event originating with software command, external digital
trigger. The Timebase is a clock provided to the ADC and
acquisition engine for essential timing. The Timebase is from an
onboard syn-thesizer. To achieve different sampling rates, a scan
interval coun-ter is used.
Using the post-trigger mode as an example, as shown, when a
trigger is accepted by the digitizer, the acquisition engine com-
mences acquisition of data from ADC, and stores the sampled
data to the onboard FIFO. When FIFO is not empty, data will be
transferred to system memory immediately through the DMA
engine. The sampled data is generated continuously at the rising
edge of Timebase according to the scan interval counter setting.
When sampled data reaches a specified value, in this example
256, acquisition ends.
ADC
X6
Multiplier
PLL
For ADC
State machine
For ADC
Data Bus
80MHz
480MHz
FPGA
ADC Output
80MHz
Onboard
80MHz
Oscillator