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Using a high-level programming library for high speed DMA data acquisition, the sampling
period and the number of conversions needs simply to be assigned into specified counters.
After the AD trigger condition is met, the data will be transferred to the system memory by
the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows, Linux, or other, it is difficult
to allocate a large continuous memory block. Therefore, the bus controller provides DMA
transfer with scatter-gather function to link non-contiguous memory blocks into a linked list
so users can transfer large amounts of data without being limited by memory limitations.
In non-scatter-gather mode, the maximum DMA data transfer size is 2 MB double words (8
MB bytes); in scatter-gather mode, there is no limitation on DMA data transfer size except
the physical storage capacity of the system.
Users can also link descriptor nodes circularly to achieve a multi-buffered DMA. Figure 3-2
illustrates a linked list comprising three DMA descriptors. Each descriptor contains a PCI
address, PCI dual address, a transfer size, and the pointer to the next descriptor. PCI address
and PCI dual address support 64-bit addresses which can be mapped into more than 4 GB of
address space, but the subsequent descriptor address must be less than 4GB.
Local Memory
( FIFO)
PCI Express Bus
First PCI Address
First Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
Figure 3-2: Linked List of PCI Address DMA Descriptors
