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3.3.3 External Clock from PXI Interfaces
The PCI/PXI-69816/26/46 can receive timebase via one of the PXI Trigger Bus lines by
software selection. The eight PXI Trigger Bus lines (PXI_TRIG[0..7]) provide inter-module
synchronization and communication. Note that this function is only available when the PCI/
PXI-69816/26/46 is in a PXI system. It’s not supported when PCI/PXI-69816/26/46 is in a
Compact PCI system.
When the PCI/PXI-69816/26/46 is plugged into a generic peripheral slot in a PXI system, it
can receive timebase from PXI_STAR. The PXI_STAR signal comes from star trigger controller
is matched in propagation delay within 1 ns and the delay from star trigger slot to peripheral
slot is less than 5 ns. According these hardware features, the PCI/PXI-69816/26/46 can
achieve very good synchronization performance when using PXI_STAR as timebase clock
source. Note that the function is only available when the PCI/PXI-698x6 is in a PXI system.
It’s not supported when the PCI/PXI-69816/26/46 is in a Compact PCI system.
3.3.4 Sampling Rate Control
By specifying different scan interval counter (24-bit) value, different sampling rate can be
achieved. The following formula determines the ADC sampling rate.
Sampling Rate = TIMEBASE / Scan Intrv
Where Scan Intrv is scan interval counter, value can be 1, 2, 3, 4… 2
24
- 1.
Refer to Figure 3-6 for detail timing.
TIMEBASE
DATA
D1
Acquisition
In Progress
Trigger
Acquisition starts right after this clock edge
D1
ScanIntrv = 1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D2
D3
D4
D5
D6
D1
4
D
3
D
2
D
ScanIntrv = 2
ScanIntrv = 3
Figure 3-6: Configuring Different Sampling Rate of a Digitizer.
3.3.5 Timebase Exporting
The PCI/PXI-69816/26/46 can export timebase to one of the eight PXI trigger bus lines.
By software programming, you can pick up a trigger line to transmit timebase clock. This
feature is very useful when synchronize to multiple measurement modules.
