JYTEK NuDAQ PCI-69222, User Manual

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36 Operation Theory
The four remaining scans are not performed until the trigger
signal is disasserted again. The process repeats until the
specified amount of retrigger signals are detected.
The total acquired data length = NumChan_counter
*PSC_counter.
Figure 4-7: Gated Trigger with Finite Scan Acquisition
Bus-mastering DMA Data Transfer
In programmable scan acquisition mode, the PCI-69222/PCI-
69223 supports bus-mastering DMA data transfer. PCI bus-
mastering DMA is necessary for high speed DAQ in order to utilize
the maximum PCI bandwidth. The bus-mastering controller
controls the PCI bus when it becomes the master. Bus mastering
reduces the size of the onboard memory and reduces CPU
loading since data is directly transferred to the system memory
with no host CPU intervention.
Bus-mastering DMA provides the fastest data transfer rate on PCI-
bus. Once the analog input operation starts, control returns to your
program. The hardware temporarily stores the acquired data in the
onboard AD Data FIFO, then transfers the data to a user-defined DMA
buffer memory in the computer. Note that even when the acquired data
length is less than the Data FIFO, the AD data is not kept in the Data FIFO
but rather directly transferred to the host memory by the bus-mastering
DMA.