Jäger ADwin-Pro, System And Hardware Description

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Pro I: Analog Input Modules
Pro-AIn-32/16 Rev. B
ADwin
62
ADwin-Pro Hardware, manual version 2.9, June 2006
Fig. 107 – Pro-AIn-32/16 Rev. B : Board and front panel
Fig. 105 – Pro-AIn-32/16 Rev. B : Pin
assignment single-ended
Fig. 106 – Pro-AIn-32/16 Rev. B : Pin
assignment differential
ANALOG IN 17
ANALOG IN 18
ANALOG IN 19
ANALOG IN 20
ANALOG IN 21
ANALOG IN 22
ANALOG IN 23
ANALOG IN 24
ANALOG IN 25
ANALOG IN 26
ANALOG IN 27
ANALOG IN 28
ANALOG IN 29
ANALOG IN 30
ANALOG IN 31
ANALOG IN 32
AGND
EVENT IN
ANALOG IN 1
ANALOG IN 2
ANALOG IN 3
ANALOG IN 4
ANALOG IN 5
ANALOG IN 6
ANALOG IN 7
ANALOG IN 8
ANALOG IN 9
ANALOG IN 10
ANALOG IN 11
ANALOG IN 12
ANALOG IN 13
ANALOG IN 14
ANALOG IN 15
ANALOG IN 16
AGND
RESERVED
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ANALOG IN 1 (-)
ANALOG IN 2 (-)
ANALOG IN 3 (-)
ANALOG IN 4 (-)
ANALOG IN 5 (-)
ANALOG IN 6 (-)
ANALOG IN 7 (-)
ANALOG IN 8 (-)
ANALOG IN 17 (-)
ANALOG IN 18 (-)
ANALOG IN 19 (-)
ANALOG IN 20 (-)
ANALOG IN 21 (-)
ANALOG IN 22 (-)
ANALOG IN 23 (-)
ANALOG IN 24 (-)
AGND
EVENT IN
ANALOG IN 1 (+)
ANALOG IN 2 (+)
ANALOG IN 3 (+)
ANALOG IN 4 (+)
ANALOG IN 5 (+)
ANALOG IN 6 (+)
ANALOG IN 7 (+)
ANALOG IN 8 (+)
ANALOG IN 17 (+)
ANALOG IN 18 (+)
ANALOG IN 19 (+)
ANALOG IN 20 (+)
ANALOG IN 21 (+)
ANALOG IN 22 (+)
ANALOG IN 23 (+)
ANALOG IN 24 (+)
AGND
RESERVED
DGND
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19AD0102
A0 A1 A2 A3 A4 A5 A6 A7
74LS
19
ON DIP
1 2 3 4 5 6 7 8
FPGA
A42MX16
D
G
407D
J
D
G
407D
J
D
G
407D
J
DC/DC CONVERTER
IN 5V OUT ±15V / ±65mA
DC/DC CONVERTER
IN 5V OUT ±5V / ±300mA
LT
C
1605C
S
W
MA
X
6225
D
S
1867
C
1-
100
P
G
A
206U
035
AIN32/16RB
ANALOG
INPUT